Embedded memories are critical in processor design since they strongly impact the area, power consumption and performance of the system. For the Angstrom Project, PEP-Core and the main processor require on-chip caches that are designed using SRAM blocks and these caches necessitate different design considerations. A voltage-scalable SRAM that is capable of operating from nominal voltage down to sub-threshold region is being built investigating possible bit-cell designs (6T/8T), read and write assist techniques, optimum WL/BL voltage selection and offset compensation.

Students: Yildiz Sinangil, Sunghyun Park