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Alexander T. Ishii, Charles E. Leiserson, and Marios C. Papaefthymiou. Optimizing two-phase, level-clocked circuitry. Journal of the ACM, 44(1):148-199, January 1997. [BibTeX entry]

We investigate two strategies for reducing the clock period of a two-phase, level-clocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edge-triggered latches into a faster level-clocked one.

We model a two-phase circuit as a graph G = (V, E) whose vertex set V is a collection of combinatorial logic blocks, and whose edge set E is a set of interconnections. Each interconnection passes through zero or more latches, where each latch is clocked by one of the two periodic, nonoverlapping waveforms, or phases.

We give efficient polynomial-time algorithms for problems involving the timing verification and optimization of two-phase circuitry. Included are algorithms for

We give fully polynomial-time approximation schemes for clock period minimization, within any given relative error epsilon > 0, by The first two of these approximation algorithms can be used to obtain the optimum clock period in the special case where all propagation delays are integer.

We generalize most of the results for two-phase clocking schemes to simple multiphase clocking disciplines, including ones with overlapping phases. Typically, the algorithms to verify and optimize the timing of k-phase circuitry are at most a factor of k slower than the corresponding algorithms for two-phase circuitry.

Our algorithms have been implemented in TIM, a timing package for two-phase, level-clocked circuitry developed at MIT.

The abstract is also available as a LaTeX file, a DVI file, or a PostScript file.

Categories and Subject Descriptors: B.6.3 [Logic Design]: Design Aids; B.7 [Integrated Circuits]; F.2 [Analysis of Algorithms and Problem Complexity]

General Terms: Algorithms, Design

Additional Key Words and Phrases: Clock tuning, level-clocked circuitry, multiphase clocking, retiming, timing analysis and optimization, VLSI

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