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[MUSIC PLAYING]

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SPEAKER 1: University
Video Communications,

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with the sponsorship
of MCC, welcomes you

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to this edition of the
Distinguished Lecture Series;

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Leaders in Computer Science
and Electrical Engineering.

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Dennis Herrell, Vise
President and program director

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of MCC's Semiconductor Packaging
and Interconnect Program,

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joined MCC in 1985 after
a distinguished 21 year

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career at IBM.

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He has a BS in physics from
Imperial College of Science

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and Technology London
and a PhD in physics

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from Cambridge University.

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In this lecture, Dr Herrell
sets the technical and economic

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goals for advanced
packaging, making the point

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that future chip development is
dependent upon the development

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of packaging technology.

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He outlines the
critical considerations

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for packaging design in the
90's, illustrating his talk

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with MCC developments like
the multi-chip module.

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Dennis Herrell.

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DENNIS HERRELL: Packaging
and interconnect technology

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has been one of the areas
of most exciting work

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in the recent years.

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Chips need to be
connected into systems,

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and this is the area that
packaging and interconnect

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tries to cover.

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Chip technology has been
improving dramatically through

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the 1980's, and that improvement
is going to continue through

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the 1990's.

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We're going to move
to finer and finer

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line technologies of the chip.

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We're presently
working in the domain

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of maybe 1 micron, 0.8
micron, through the line

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widths on these chips.

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And we're going to get to
much smaller line widths

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as we go through the
1990's, so that we're

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down to maybe 1/3 of the micron
by the time we get to the year

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2000.

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Larger chips will
be coming along.

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At the present moment,
chips are only less

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than a centimeter on this side.

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They're going to be 2 or maybe
even 3 centimeters by the year

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2000.

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So that is where chip
technology is going to take us.

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And the packaging
technology has to keep pace

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with that rapid demand--

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that rapid improvement
in the chip technology.

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What we really also
need to understand

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is where the computer
technology is

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going to go in the 1990's,
because we, on the one hand,

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know where the chip
is going to go,

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but we really have
to understand where

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the computers are going to go.

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Because the packaging and
interconnect technology really

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produces the bridge between
the chip, on the one hand,

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and how you put them in the
computer, on the other hand.

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Processing performance
demands are

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going to continue to increase.

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People are going to
want to have more

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storage on their computers.

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They're going to want
fast interactive systems.

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There's going to be more and
more demand for animation.

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There's going to be more
and more demand for speech

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processing; computers that
can recognize your speech,

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computers that can
speak back to you.

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And there's going to
be more and more stress

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on the accessing of large
pieces of information,

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large databases.

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So there's going to be a lot of
effort in the area of storage

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and networking as we
go through the 90's

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and into the new century.

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So we really want to look
now at what advances are

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needed in the packaging area.

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So we talked about larger chips.

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They're going to be faster.

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They're going to be
more power hungry.

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Now it turned out in the 1980's
that with the rapid improvement

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in the chip technology the
packaging technology really

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took a backseat.

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Everybody and their
uncle working on chips

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and the packaging technology
people were kind of

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relegated to the back
room, and as soon

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as the chips came
out of the door

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they're expected
to package them.

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And that rapid development and
chip technologies and designs

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is going to continue through
the 1990's, but people are now

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beginning to wake up to the fact
that system performance is not

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just achieved by
making better chips.

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You have to keep the
packaging technology in step

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with the improvements that
are happening in the chips.

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Here's an example of what's
happened in the past.

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We started out with
systems, or chips,

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which maybe were made with 10
micron lithography technology.

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With systems that are
made with chips like that,

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maybe the clock frequency was
only as high as 1 megahertz,

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and the overall portion
of the cycle that

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was involved with
the packaging delays,

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or the overall power that
the packaging used up

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in that system, was only
maybe about 10% or 15%

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of the overall system.

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But as we're now moving
to 1/2 micron technology,

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and we're looking
at systems that

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might be running as
fast as 100 megahertz,

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we've got to contemplate
that the packaging is going

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to take up maybe
1/2 or even larger

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portion of both the power and
the delay within the system.

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And this is the challenge that
the packaging engineer now

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has to try and see what new
innovations he can bring

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that is going to make
the package component

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delays and the package power
portion still, for example,

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keep it below 50%.

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So with these things
in mind, let's overview

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some of the driving
forces behind the things

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that we have to do in
the packaging arena.

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I've talked about the chip.

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Let's go back and think a
little bit more about that chip.

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Some people call it
the integrated circuit.

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Most of the chips out
there at the present moment

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a silicon technology chips.

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We hear of acronyms like
CMOS, Bipolar, BICMOS.

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These are the standard
chip technologies

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that we have at
the present moment.

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They're dramatically
improving in performance.

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We also hear a little bit
about gallium arsenide,

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and there is a chance
that gallium arsenide

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will become a
significant driving

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force by the end of the decade.

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But at the present moment, it's
silicon and principally CMOS

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technology.

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These chips are presently made
as relatively small bricks

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about 1 centimeter by
1 centimeter on a side

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and less than 1
millimeter thick.

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But when you look inside
a PC, as we're now doing,

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you don't see chips per se.

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What you see in the packaged
result of the chips.

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The chips are
inside these objects

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that are scattered about
on this board here.

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What we really need to do
is, at the present moment,

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look at what those
technologies are.

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Now this slide is an alphabet
soup of the types of acronyms

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that the packaging engineers
are presently using today.

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Most of the PCs,
for example, are

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made by putting dual in line
package, that's DIP, on PCB's,

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printed circuit boards.

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And there are a number of ways
of doing that, but typically

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you mount the device and the
actual chip, that we're talking

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about, is that green rectangle
within that protective box,

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as it were.

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And that green rectangle
box can either be mounted

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on the surface of the printed
circuit board, as with surface

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mount technology,
SMT, or it can be

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plugged through holes in
the printed circuit board

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as is with PTH, pin
through hole technology.

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Now, there are many other
ways of packaging device other

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than dual inline package.

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There's a small outline package,
or there's pin grid array, PGA,

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or there's quad flat pack, QFP.

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These are the kinds of
packaging technologies

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that are presently available.

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But, what we need to
do is look forward

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to new packaging
technologies that

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are going to enable much
denser connections coming

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from these chips.

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This is an example
of TAB technology,

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for tape automated
bonding technology,

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and this is the
kind of technology

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that we'll be talking
about in this presentation.

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So what is packaging and
interconnect technology

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after we've got this far?

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Most systems consist of an
assembly of integrated circuit

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chips.

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The chips need to
communicate to one another

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and to the outside world.

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The chips need power to work.

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They need to be cooled.

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And those chips need
to be protected.

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And this is what packaging and
interconnect technology is all

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about.

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So now let's look at the design
forces, the driving forces,

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that are involved in making the
right choices for the packaging

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and Interconnect
technology, how you

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put the chips into the system.

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It's a good idea to look where
the chip technology is headed,

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and let's look forward
to the year 2000.

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We can expect chips that will
be running with a 200 megahertz

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cycle time.

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That's compared to
where we are today

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of maybe 30 or 40
megahertz at the very best.

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We're looking forward
to larger devices.

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Instead of the 1
centimeter, we'll

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be up at 2 and maybe
even 3 centimeters.

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We're going to be looking
at more I/O, that's

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a number of pins, that's
a number of connections,

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that come off the chip.

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At the present moment, maybe
chips go up to 400 I/O.

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We'll be looking to
over 1,000 by the time

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we get to the year 2000.

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And also these chips
are going to be hotter.

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Presently chips may be
no more than 5 watts.

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Now, we're talking
about looking forward

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to having 50 watt chips.

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So we're going to be, in
summary, 10 times faster,

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maybe 2 or 3 times larger,
maybe 2 or 3 times more I/O,

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and certainly almost 10
times hotter for these chips.

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That's the challenge
that we face.

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Where the system's heading?

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Well we've already said
some things about this.

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They're going to be faster.

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They're going to
be more powerful.

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We've already seen a
progression of 5 megahertz

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to maybe 30 megahertz
with regards to PCs.

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And we've got to
ask ourselves, now,

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what's needed beyond that single
chip packaging on the printed

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circuit board, that
we've been talking about.

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Now, in the past the
supercomputer manufacturers,

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the mainframe
manufacturers, have

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found that as they
went above 50 megahertz

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for their system
clock, they needed

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to go out of the single
chip packaging and PCB.

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They needed to go to something
called multi-chip module

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technology.

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And that's what I'm
going to be talking

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about for the rest of this talk.

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Let's just look at the
microprocessor chips

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to put this all in perspective.

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Here are some historical trends
of microprocessor chips through

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the decades of the 70's and
80's, going into the 90's.

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There is no reason
at the present moment

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to not expect that this chip
technology will continue

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to improve in performance.

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And so, you can clearly
see that by the year 2000,

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the performance expectations
of microprocessors

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are going to be well
over 100 megahertz.

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There are very good cases
that it could possibly

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be over 1 gigahertz,
1,000 megahertz.

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Now the conventional single
chip packaging, it turns out,

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cannot handle the high I/O
and it's not cost effective.

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At the present moment, the
best packaging technology

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for handling high I/O is
the pin grid array, the PGA,

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and it does a
reasonably adequate job,

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but it is too expensive.

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And as we go to wanting more
and more I/O off the chip,

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that pin grid array is going to
get larger and larger and more

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and more expensive.

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We're finding, therefore, that
this high speed single chip

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packaging is too costly.

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And, furthermore, the
printed circuit board

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that this chip technology,
this single chip packaging

250
00:11:28,290 --> 00:11:30,840
technology, has
to connect to also

251
00:11:30,840 --> 00:11:34,140
becomes too costly
and too complex.

252
00:11:34,140 --> 00:11:38,580
Let's look at how much area
the chip packages take up

253
00:11:38,580 --> 00:11:40,500
on the printed circuit board.

254
00:11:40,500 --> 00:11:43,690
And, so, on this graph
here on the left hand side,

255
00:11:43,690 --> 00:11:44,970
we have the card area.

256
00:11:44,970 --> 00:11:50,040
You could think of that is the
area occupied by the packaged

257
00:11:50,040 --> 00:11:52,170
chip on the board,
and, as you see,

258
00:11:52,170 --> 00:11:57,060
it runs from 0 to 25
square centimeters.

259
00:11:57,060 --> 00:12:00,360
And, on the horizontal axis,
we have a logarithmic scale

260
00:12:00,360 --> 00:12:02,500
of the package pin count.

261
00:12:02,500 --> 00:12:05,580
You can see from this graph
that, really, the dual inline

262
00:12:05,580 --> 00:12:09,810
package is lost, if you want
to have more than 64 I/O

263
00:12:09,810 --> 00:12:11,170
from a particular chip.

264
00:12:11,170 --> 00:12:14,710
It just begins to consume
too much area on the board,

265
00:12:14,710 --> 00:12:19,350
and so you have to move to some
of the packaging technologies

266
00:12:19,350 --> 00:12:21,990
further to the
right on this graph.

267
00:12:21,990 --> 00:12:25,660
Pin grid array, there, is in the
middle of that band, broadband,

268
00:12:25,660 --> 00:12:26,160
there.

269
00:12:26,160 --> 00:12:31,620
And, certainly, pin grid
array can fairly effectively

270
00:12:31,620 --> 00:12:36,720
package devices that have
maybe 250 maybe even 500 I/O.

271
00:12:36,720 --> 00:12:39,060
But if you really want to
push off the right hand

272
00:12:39,060 --> 00:12:41,850
side of this graph, as it looks
that chip technologies are

273
00:12:41,850 --> 00:12:43,710
going to, then
you're going to have

274
00:12:43,710 --> 00:12:47,760
to look in other directions for
the connection and packaging

275
00:12:47,760 --> 00:12:48,790
technology.

276
00:12:48,790 --> 00:12:51,390
And that's where I think
that TAB technology is going

277
00:12:51,390 --> 00:12:52,830
to play an important role.

278
00:12:52,830 --> 00:12:58,140
That's that T-A-B there
for tape automated bonding.

279
00:12:58,140 --> 00:13:00,900
And that board
that I referred to,

280
00:13:00,900 --> 00:13:03,990
the way that you get the
interconnectivity in the board,

281
00:13:03,990 --> 00:13:06,240
that is all the wires
that need to connect

282
00:13:06,240 --> 00:13:10,110
between these packaged chips,
the present way of doing that

283
00:13:10,110 --> 00:13:13,240
is to increase the number
of layers in the board.

284
00:13:13,240 --> 00:13:16,800
This is a historical trend
showing through the late 70's

285
00:13:16,800 --> 00:13:20,550
and through the 80's, how the
number of layers in the board

286
00:13:20,550 --> 00:13:22,990
has increased,
that's the blue line.

287
00:13:22,990 --> 00:13:26,340
And you can see that
as we entered 1990,

288
00:13:26,340 --> 00:13:28,530
we were getting
close to 100 layers

289
00:13:28,530 --> 00:13:30,660
within the printed
circuit board.

290
00:13:30,660 --> 00:13:33,690
The board also gets
substantially thicker and much

291
00:13:33,690 --> 00:13:36,600
more difficult to make, because
one way of making the printed

292
00:13:36,600 --> 00:13:40,080
circuit board requires that you
drill holes through that board

293
00:13:40,080 --> 00:13:42,030
to get the connections
that run vertically

294
00:13:42,030 --> 00:13:44,730
between those layers.

295
00:13:44,730 --> 00:13:48,900
This particular technology
becomes increasingly complex

296
00:13:48,900 --> 00:13:52,240
as you can see and very
expensive as a consequence.

297
00:13:52,240 --> 00:13:56,490
We have to look for
cheaper solutions.

298
00:13:56,490 --> 00:14:01,080
Now, you may ask, why not go
to wafer scale integration?

299
00:14:01,080 --> 00:14:04,060
Why cut up these chips
into small units?

300
00:14:04,060 --> 00:14:07,110
Why not make one large big chip?

301
00:14:07,110 --> 00:14:10,110
The simple answer to that is,
at the present moment, the way

302
00:14:10,110 --> 00:14:14,460
that we see that we can go,
it's going to be too expensive.

303
00:14:14,460 --> 00:14:20,910
You cannot yield large
chips sufficiently well.

304
00:14:20,910 --> 00:14:23,430
The other problem with
wafer scale integration

305
00:14:23,430 --> 00:14:25,950
is usually different
technologies are required

306
00:14:25,950 --> 00:14:27,510
for different functions.

307
00:14:27,510 --> 00:14:31,920
You usually need a different
integrated circuit technology

308
00:14:31,920 --> 00:14:34,530
for logic, than you
do for fast cash,

309
00:14:34,530 --> 00:14:36,240
than you do for dense memory.

310
00:14:36,240 --> 00:14:39,180
And it's very difficult to come
up with an integrated circuit

311
00:14:39,180 --> 00:14:42,540
process that satisfies
all those requirements,

312
00:14:42,540 --> 00:14:45,390
such that you can put all
those kinds of functions

313
00:14:45,390 --> 00:14:46,830
on one big chip.

314
00:14:46,830 --> 00:14:49,350
That's why I don't think
wafer scale integration

315
00:14:49,350 --> 00:14:51,150
is going to be the solution.

316
00:14:51,150 --> 00:14:53,760
Even if it was, it's still
going to need a package

317
00:14:53,760 --> 00:14:56,460
to protect that wafer
from the environment,

318
00:14:56,460 --> 00:14:58,980
to connect that wafer
to the outside world,

319
00:14:58,980 --> 00:15:02,460
to provide power, and
to provide cooling.

320
00:15:02,460 --> 00:15:04,200
Let's look at the
electrical performance,

321
00:15:04,200 --> 00:15:06,510
and see what direction
that drives us,

322
00:15:06,510 --> 00:15:08,790
and to see why that
drives us in the direction

323
00:15:08,790 --> 00:15:11,670
of the multi-chip module.

324
00:15:11,670 --> 00:15:15,460
When you have a typical
operation in the machine,

325
00:15:15,460 --> 00:15:18,180
the data exits registers.

326
00:15:18,180 --> 00:15:20,430
You go through a certain
number of logic decisions

327
00:15:20,430 --> 00:15:21,600
on a number of chips.

328
00:15:21,600 --> 00:15:23,850
You may send an address
over to the memory.

329
00:15:23,850 --> 00:15:25,470
You may fetch the
data from memory,

330
00:15:25,470 --> 00:15:29,100
and then end up that cycle
by loading that information

331
00:15:29,100 --> 00:15:30,390
into a register.

332
00:15:30,390 --> 00:15:32,125
That's a typical machine cycle.

333
00:15:32,125 --> 00:15:33,750
That's the type of
thing that has to be

334
00:15:33,750 --> 00:15:36,420
done in one tick of the clock.

335
00:15:36,420 --> 00:15:39,300
Now, if you look at
present mainframe systems,

336
00:15:39,300 --> 00:15:43,410
back in the early 80's, IBM
introduced a 3033 machine,

337
00:15:43,410 --> 00:15:45,600
and that was built in
single chip packaging

338
00:15:45,600 --> 00:15:46,980
on printed circuit board.

339
00:15:46,980 --> 00:15:50,190
And that had a cycle
time of 57 nanoseconds.

340
00:15:50,190 --> 00:15:52,115
In order for them to
be able to come out

341
00:15:52,115 --> 00:15:53,490
with their next
machine, which is

342
00:15:53,490 --> 00:15:57,660
the 3081, with a substantially
improved cycle time,

343
00:15:57,660 --> 00:16:00,120
down to 26 nanoseconds,
they really

344
00:16:00,120 --> 00:16:02,850
had to shrink the package
component of the delay.

345
00:16:02,850 --> 00:16:07,020
And they did that by going to
multi-chip module technology.

346
00:16:07,020 --> 00:16:08,610
Now, why did they
have to shrink?

347
00:16:08,610 --> 00:16:11,640
Why did they have to go
to multi-chip modules?

348
00:16:11,640 --> 00:16:13,950
To get an answer to that
we have to introduce

349
00:16:13,950 --> 00:16:17,790
into this discussion
the velocity of light,

350
00:16:17,790 --> 00:16:19,950
the rate at which
signals can propagate

351
00:16:19,950 --> 00:16:21,480
throughout the system.

352
00:16:21,480 --> 00:16:24,390
You're probably well aware
that the velocity of light

353
00:16:24,390 --> 00:16:29,040
is such that in one
nanosecond light in free space

354
00:16:29,040 --> 00:16:32,310
can travel about 30
centimeters or one foot.

355
00:16:32,310 --> 00:16:34,390
Now, usually in
electronic systems

356
00:16:34,390 --> 00:16:36,390
that we're dealing with,
the dielectric constant

357
00:16:36,390 --> 00:16:40,440
is in the range of maybe 3
to 5 or maybe as high as 10.

358
00:16:40,440 --> 00:16:43,950
And so, the actual speed
of signal propagation

359
00:16:43,950 --> 00:16:46,290
within computer systems
is usually about a third

360
00:16:46,290 --> 00:16:48,030
of the speed of
light, which means

361
00:16:48,030 --> 00:16:52,380
that you can go about 10
centimeters in 1 nanosecond.

362
00:16:52,380 --> 00:16:55,460
So, if you really want to have
systems that are running fast,

363
00:16:55,460 --> 00:16:57,750
that have small delays
between the components,

364
00:16:57,750 --> 00:17:01,470
you have to make that computer
system relatively small.

365
00:17:01,470 --> 00:17:05,030
Otherwise, you'll just be losing
out to the velocity of light.

366
00:17:05,030 --> 00:17:07,670
Now, we need to look
at the signal fidelity

367
00:17:07,670 --> 00:17:10,339
as we send signals
between the chips.

368
00:17:10,339 --> 00:17:13,160
If the risetime of the signal,
the rate at which the signal

369
00:17:13,160 --> 00:17:17,329
rises from at 0 to 1 state,
is substantially longer

370
00:17:17,329 --> 00:17:20,089
than the path length,
then you, essentially,

371
00:17:20,089 --> 00:17:22,910
end up by just charging
the output capacitance,

372
00:17:22,910 --> 00:17:24,619
or the capacitance of the net.

373
00:17:24,619 --> 00:17:25,980
I'll give an example here.

374
00:17:25,980 --> 00:17:29,300
If the net is 5 picofarads
and the output impedance

375
00:17:29,300 --> 00:17:32,720
of the device is 1,000 ohms,
then the RC time constant

376
00:17:32,720 --> 00:17:34,830
is going to be
about 5 nanoseconds.

377
00:17:34,830 --> 00:17:37,010
And this is shown
diagrammatically here.

378
00:17:37,010 --> 00:17:42,530
On the left hand side, we
have a driver shown a Thevenin

379
00:17:42,530 --> 00:17:46,040
equivalent for that driver
that steps up in voltage,

380
00:17:46,040 --> 00:17:49,670
but the output, as
indicated, rises

381
00:17:49,670 --> 00:17:51,470
with the time constant of RC.

382
00:17:51,470 --> 00:17:54,110
We have a typical
exponential rise

383
00:17:54,110 --> 00:17:57,650
of the signal at the receiver
end, which is the right hand

384
00:17:57,650 --> 00:18:00,710
side of this graphic.

385
00:18:00,710 --> 00:18:03,440
Now, as we go to faster
signal rise times,

386
00:18:03,440 --> 00:18:06,440
we've got to look at
transmission line effects.

387
00:18:06,440 --> 00:18:08,780
Now, that's probably
not necessary for CMOS.

388
00:18:08,780 --> 00:18:10,790
CMOS typically, at
the present moment,

389
00:18:10,790 --> 00:18:14,520
still has a few nanoseconds
for its risetime.

390
00:18:14,520 --> 00:18:17,270
But, ECL is a sub
nanosecond technology.

391
00:18:17,270 --> 00:18:19,970
ECL is emitter
coupled logic, and it

392
00:18:19,970 --> 00:18:24,140
has rise times of the order
of 100 or 200 picoseconds,

393
00:18:24,140 --> 00:18:25,520
at the present moment.

394
00:18:25,520 --> 00:18:28,310
Both of these technologies are
going to get faster as we go

395
00:18:28,310 --> 00:18:29,180
through the 90's.

396
00:18:29,180 --> 00:18:31,550
And CMOS is very
rapidly going to get

397
00:18:31,550 --> 00:18:34,560
into the subnanosecond
risetime regime.

398
00:18:34,560 --> 00:18:39,200
And so, the issues of sending
signals on transmission lines

399
00:18:39,200 --> 00:18:43,190
is going to be important for
both bipolar technologies

400
00:18:43,190 --> 00:18:46,130
like ECL as well
as CMOS technology.

401
00:18:46,130 --> 00:18:49,670
So, let's think about
transmission lines.

402
00:18:49,670 --> 00:18:51,440
We're talking about
sending signals

403
00:18:51,440 --> 00:18:54,410
that have risetimes that are
short compared to the length.

404
00:18:54,410 --> 00:18:57,590
For example, a 200
picosecond risetime signal

405
00:18:57,590 --> 00:19:00,260
going into a line 10 centimeters
long, which would have

406
00:19:00,260 --> 00:19:02,540
a delay of one nanoseconds.

407
00:19:02,540 --> 00:19:05,870
Now we're sending
energy into that line,

408
00:19:05,870 --> 00:19:10,130
and that energy can echo around,
and that causes some problems

409
00:19:10,130 --> 00:19:11,780
that we're going to talk about.

410
00:19:11,780 --> 00:19:14,330
Generally speaking,
though, we're

411
00:19:14,330 --> 00:19:20,510
usually OK to assume a TEM mode
for the transmission lines,

412
00:19:20,510 --> 00:19:22,130
at least at the present moment.

413
00:19:22,130 --> 00:19:25,010
When we start thinking about
going above 1 gigahertz,

414
00:19:25,010 --> 00:19:29,280
maybe we even have to be
more sophisticated than that.

415
00:19:29,280 --> 00:19:31,750
So here's a transmission line.

416
00:19:31,750 --> 00:19:35,320
We send a signal from the left
hand side, here, and the signal

417
00:19:35,320 --> 00:19:39,310
as it arrives at the right at
the receiver sometime later,

418
00:19:39,310 --> 00:19:41,980
just given by the delay
of the transmission line.

419
00:19:41,980 --> 00:19:45,070
But, generally speaking, with
an ideal transmission line,

420
00:19:45,070 --> 00:19:47,740
the risetime of the
signal is preserved

421
00:19:47,740 --> 00:19:51,020
as we send that signal
through the transmission line.

422
00:19:51,020 --> 00:19:52,360
So that's the ideal system.

423
00:19:52,360 --> 00:19:55,540
That's what we would like to
see in our computer systems

424
00:19:55,540 --> 00:19:57,670
that we put together.

425
00:19:57,670 --> 00:20:00,100
What happens in reality
is we get a mess,

426
00:20:00,100 --> 00:20:01,720
looking something like this.

427
00:20:01,720 --> 00:20:07,310
The waveforms that get sent
and received are very messy.

428
00:20:07,310 --> 00:20:14,140
They have lots of bumps and
dips, reflections, echoes.

429
00:20:14,140 --> 00:20:18,340
This is a significant concern
in designing a system,

430
00:20:18,340 --> 00:20:20,860
because these bumps and
dips on the waveforms

431
00:20:20,860 --> 00:20:25,530
can cause erroneous
switching of devices.

432
00:20:25,530 --> 00:20:27,910
We have to understand
where that comes from.

433
00:20:27,910 --> 00:20:30,500
Now, when you really look
at the transmission lines,

434
00:20:30,500 --> 00:20:33,830
you're sending a signal on
down, let's say, line 1.

435
00:20:33,830 --> 00:20:37,200
But, you have another line
in close proximity to that.

436
00:20:37,200 --> 00:20:41,480
But those transmission lines are
not independent of one another,

437
00:20:41,480 --> 00:20:43,700
they are coupled to one another.

438
00:20:43,700 --> 00:20:46,040
And I've shown very
simply here the coupling,

439
00:20:46,040 --> 00:20:48,250
in terms of a mutual
inductance, L sub

440
00:20:48,250 --> 00:20:51,530
M, and the mutual
capacitance C sub M.

441
00:20:51,530 --> 00:20:54,680
And these inductances
and capacitances,

442
00:20:54,680 --> 00:20:59,210
these mutual terms, need to be
compared to the self inductance

443
00:20:59,210 --> 00:21:03,032
and self capacitance of the
transmission line L S and C S.

444
00:21:03,032 --> 00:21:06,570
Now this coupling between
two parallel lines,

445
00:21:06,570 --> 00:21:09,440
which occurs very
typically within

446
00:21:09,440 --> 00:21:12,980
the interconnect technology
between the chips,

447
00:21:12,980 --> 00:21:13,970
leads to crosstalk.

448
00:21:13,970 --> 00:21:15,830
And there are two
forms of crosstalk.

449
00:21:15,830 --> 00:21:18,200
One is forward wave
crosstalk, where

450
00:21:18,200 --> 00:21:22,040
you get a signal that
propagates on the quiet line

451
00:21:22,040 --> 00:21:25,350
and that signal is a
blip, a discontinuity,

452
00:21:25,350 --> 00:21:28,670
a jump in voltage,
that propagates

453
00:21:28,670 --> 00:21:34,250
along the quiet line in parallel
with the driver line signal.

454
00:21:34,250 --> 00:21:39,920
And the magnitude of that
foward wave crosstalk,

455
00:21:39,920 --> 00:21:42,240
is determined by a
difference between

456
00:21:42,240 --> 00:21:45,030
the inductive
mutual coupling and

457
00:21:45,030 --> 00:21:46,800
the capacitive mutual coupling.

458
00:21:46,800 --> 00:21:50,400
So, if somehow you can
engineer that those two

459
00:21:50,400 --> 00:21:53,370
terms in parentheses, there,
the first and second term

460
00:21:53,370 --> 00:21:56,970
are equal, then you can actually
cancel out the forward wave

461
00:21:56,970 --> 00:21:58,920
crosstalk.

462
00:21:58,920 --> 00:22:00,690
The other form of
crosstalk is backward

463
00:22:00,690 --> 00:22:04,860
wave crosstalk, which appears
as a step on the quiet line that

464
00:22:04,860 --> 00:22:07,530
stretches out behind the
propagating edge on the driving

465
00:22:07,530 --> 00:22:08,460
line.

466
00:22:08,460 --> 00:22:11,790
Here, I show the equation
for backward wave crosstalk.

467
00:22:11,790 --> 00:22:15,090
And, now you see those two
terms in the parentheses

468
00:22:15,090 --> 00:22:16,750
are added together.

469
00:22:16,750 --> 00:22:19,410
And, so when we have
no way of canceling out

470
00:22:19,410 --> 00:22:21,540
this backward wave
crosstalk, the only way

471
00:22:21,540 --> 00:22:24,840
that we can reduce the magnitude
of the backward wave crosstalk

472
00:22:24,840 --> 00:22:27,750
is to reduce Lm and Cm.

473
00:22:27,750 --> 00:22:29,670
And the best way
of doing that is

474
00:22:29,670 --> 00:22:32,190
to move those lines
further apart, which

475
00:22:32,190 --> 00:22:36,870
runs counter to our requirement
of trying to get as many lines

476
00:22:36,870 --> 00:22:40,080
into a smaller
space as possible.

477
00:22:40,080 --> 00:22:44,370
What I show here is
just one simple step

478
00:22:44,370 --> 00:22:47,370
that is propagated
along one line, that's

479
00:22:47,370 --> 00:22:51,060
the purple outgoing
waveform on the top graph,

480
00:22:51,060 --> 00:22:55,310
and the received signal
at the end of that line.

481
00:22:55,310 --> 00:22:57,500
You see there is still
a significant amount

482
00:22:57,500 --> 00:22:58,610
of distortion here.

483
00:22:58,610 --> 00:23:00,260
What I'm trying to
do with this slide

484
00:23:00,260 --> 00:23:04,070
is to show where these
two crosstalks come in

485
00:23:04,070 --> 00:23:05,410
and have an effect.

486
00:23:05,410 --> 00:23:07,460
If you look below, we're
looking at the signals

487
00:23:07,460 --> 00:23:09,710
on the sending end
and the receiving

488
00:23:09,710 --> 00:23:12,080
end of the quiet line.

489
00:23:12,080 --> 00:23:16,220
The received signal, the
orange waveform with a blip,

490
00:23:16,220 --> 00:23:21,470
is the forward wave crosstalk
that appears at the far end.

491
00:23:21,470 --> 00:23:24,530
The increasing signal
at the near end,

492
00:23:24,530 --> 00:23:28,580
which is that turquoise color,
is the backward wave crosstalk

493
00:23:28,580 --> 00:23:32,450
that's observed at the
sending end on the quiet line.

494
00:23:32,450 --> 00:23:34,640
These are the types
of effects that

495
00:23:34,640 --> 00:23:37,250
have to be taken into
account in designing

496
00:23:37,250 --> 00:23:39,650
the interconnect
technology, that connects

497
00:23:39,650 --> 00:23:42,410
the signals between the chips.

498
00:23:42,410 --> 00:23:44,420
Now in addition to
just the transmission

499
00:23:44,420 --> 00:23:46,040
line effects that
I've talked about,

500
00:23:46,040 --> 00:23:48,500
we have to consider
the discontinuities

501
00:23:48,500 --> 00:23:49,880
in that transmission line.

502
00:23:49,880 --> 00:23:53,630
And those discontinuities
come through vertical veirs

503
00:23:53,630 --> 00:23:57,080
within the interconnect
technology, or, in particular,

504
00:23:57,080 --> 00:23:59,480
the connections that are
made between the chip

505
00:23:59,480 --> 00:24:02,630
and the interconnect,
or the connections

506
00:24:02,630 --> 00:24:06,770
that are made between one
portion of the interconnect

507
00:24:06,770 --> 00:24:08,940
and the next as we go
through a connector.

508
00:24:08,940 --> 00:24:11,480
So we're talking about the
discontinuities associated

509
00:24:11,480 --> 00:24:14,337
with chip connections,
connectors, and veirs

510
00:24:14,337 --> 00:24:15,920
in the interconnect.

511
00:24:15,920 --> 00:24:17,990
And these
discontinuities usually

512
00:24:17,990 --> 00:24:22,730
look like an inductive, L, or
a capacitive, C, discontinuity

513
00:24:22,730 --> 00:24:24,800
in an otherwise
relatively uniform

514
00:24:24,800 --> 00:24:27,530
characteristic impedance, Z 0.

515
00:24:27,530 --> 00:24:31,430
Now it turns out that usually
the inductive discontinuities

516
00:24:31,430 --> 00:24:35,240
in the system by far outweigh
the capacitive discontinuities

517
00:24:35,240 --> 00:24:38,880
in the system, as I
indicated at the bottom.

518
00:24:38,880 --> 00:24:42,200
So let's just look at the
effects of inductive coupling

519
00:24:42,200 --> 00:24:44,780
between discontinuities
and let's

520
00:24:44,780 --> 00:24:46,490
consider, for the
present moment,

521
00:24:46,490 --> 00:24:48,890
two connections
that go to a chip.

522
00:24:48,890 --> 00:24:51,290
I've got one connection
where I'm sending a signal.

523
00:24:51,290 --> 00:24:55,140
I've got a parallel connection,
where at the present moment,

524
00:24:55,140 --> 00:24:58,190
we can assume it is
a quiet connection.

525
00:24:58,190 --> 00:25:00,140
Now on the driving
line, I have a rate

526
00:25:00,140 --> 00:25:03,290
of change of current
d I by d t, there,

527
00:25:03,290 --> 00:25:05,690
but on the sensing
or the quiet line

528
00:25:05,690 --> 00:25:09,210
I induce into that,
essentially like a transformer,

529
00:25:09,210 --> 00:25:13,730
a coupled signal, d V s, as
I've indicated in this slide.

530
00:25:13,730 --> 00:25:17,420
Now, we can relate d V S to the
driving current rate of change

531
00:25:17,420 --> 00:25:19,340
through the mutual
inductance, and that's

532
00:25:19,340 --> 00:25:22,100
what's shown at the
bottom of this slide.

533
00:25:22,100 --> 00:25:26,660
Now we can get an idea of
the magnitude of these terms

534
00:25:26,660 --> 00:25:29,990
by looking at some
simple types of signals.

535
00:25:29,990 --> 00:25:32,450
And just for
simplicity, let's assume

536
00:25:32,450 --> 00:25:35,750
that the driving signal is
an exponentially rising step

537
00:25:35,750 --> 00:25:36,780
function.

538
00:25:36,780 --> 00:25:41,190
So, we've got V 0 e to
the minus t upon Tor.

539
00:25:41,190 --> 00:25:43,500
Now the drive
current, because we're

540
00:25:43,500 --> 00:25:47,250
dealing with a transmission line
with a characteristic impedance

541
00:25:47,250 --> 00:25:53,730
of Z 0, I d is the drive
voltage, V d divided by Z 0.

542
00:25:53,730 --> 00:25:57,390
The induced voltage
in the adjacent line,

543
00:25:57,390 --> 00:25:59,910
due to this inductive
discontinuity,

544
00:25:59,910 --> 00:26:02,740
is as shown in
the next equation.

545
00:26:02,740 --> 00:26:05,610
We've got the factor of 2
there in the denominator,

546
00:26:05,610 --> 00:26:08,640
because that disturbance
that is induced

547
00:26:08,640 --> 00:26:11,970
into this inductive
discontinuity propagates

548
00:26:11,970 --> 00:26:15,870
away in both directions,
towards the driver

549
00:26:15,870 --> 00:26:17,360
and towards the receiver.

550
00:26:17,360 --> 00:26:19,830
So that's where the
factor of 2 comes from.

551
00:26:19,830 --> 00:26:23,650
Substituting for d I by
d t in that equation,

552
00:26:23,650 --> 00:26:27,480
we now get the magnitude of
the disturb on the quiet line,

553
00:26:27,480 --> 00:26:30,592
is given by the mutual
inductance divided by 2 Z

554
00:26:30,592 --> 00:26:32,520
0 times t.

555
00:26:32,520 --> 00:26:34,560
And this t in this
particular case

556
00:26:34,560 --> 00:26:37,140
is a time constant
of the exponential.

557
00:26:37,140 --> 00:26:38,950
So if we plug some
figures in here,

558
00:26:38,950 --> 00:26:41,400
which are fairly typical,
if we think of a chip

559
00:26:41,400 --> 00:26:45,960
connection, which could be a
wire bond or a TAB connection,

560
00:26:45,960 --> 00:26:49,650
the mutual inductance might
be about 500 picohenrys.

561
00:26:49,650 --> 00:26:51,840
We'll typically
deal with systems

562
00:26:51,840 --> 00:26:54,570
of the characteristic
impedance of 50 ohms.

563
00:26:54,570 --> 00:26:57,360
And let's say we have a
risetime of the order of 500

564
00:26:57,360 --> 00:27:00,210
picoseconds, and plugging
it into that equation

565
00:27:00,210 --> 00:27:04,770
we can expect a disturbance
due to this inductive coupling

566
00:27:04,770 --> 00:27:06,750
between these discontinuities.

567
00:27:06,750 --> 00:27:09,660
We can expect a
disturbance of 1%.

568
00:27:09,660 --> 00:27:13,380
Now, that's 1% from
the line to the left.

569
00:27:13,380 --> 00:27:16,860
If there is at the same
time a simultaneous signal

570
00:27:16,860 --> 00:27:19,440
on the line to the
right, there's another 1%

571
00:27:19,440 --> 00:27:20,280
coming from that.

572
00:27:20,280 --> 00:27:23,310
And, so that these
discontinuities

573
00:27:23,310 --> 00:27:28,140
can, in principle, add
up the disturbances

574
00:27:28,140 --> 00:27:29,407
on the quiet lines.

575
00:27:29,407 --> 00:27:30,990
And this is one of
the things that you

576
00:27:30,990 --> 00:27:36,810
have to be very careful with and
is a significant factor in how

577
00:27:36,810 --> 00:27:39,885
you design the systems.

578
00:27:39,885 --> 00:27:41,760
Now while we're talking
about these inductive

579
00:27:41,760 --> 00:27:44,490
discontinuities, let's
just look at one other area

580
00:27:44,490 --> 00:27:46,740
that causes a lot of
headache, and that

581
00:27:46,740 --> 00:27:48,300
is the power delivered.

582
00:27:48,300 --> 00:27:50,670
Usually the voltage
rails that go to a chip

583
00:27:50,670 --> 00:27:53,490
are between 1 and 5 volts.

584
00:27:53,490 --> 00:27:55,860
And you require a
voltage regulation

585
00:27:55,860 --> 00:27:58,640
to be better than 10%.

586
00:27:58,640 --> 00:28:01,830
We want to avoid false
operation from power disturbs.

587
00:28:01,830 --> 00:28:03,780
Those power disturbs
are generally

588
00:28:03,780 --> 00:28:07,590
caused by the inductance of
the connection of the power

589
00:28:07,590 --> 00:28:08,670
to the chip.

590
00:28:08,670 --> 00:28:12,550
A good example of this problem
is in your home environment,

591
00:28:12,550 --> 00:28:15,060
if you don't have a very
good power distribution

592
00:28:15,060 --> 00:28:16,620
system to your house.

593
00:28:16,620 --> 00:28:19,800
Whenever the compressor on,
shall we say, your refrigerator

594
00:28:19,800 --> 00:28:24,370
turns on, it draws additional
current from the power supply.

595
00:28:24,370 --> 00:28:27,330
If you don't have a good
connection to the power supply

596
00:28:27,330 --> 00:28:29,400
there's too much
inductance in that,

597
00:28:29,400 --> 00:28:32,040
then, as that
compressor turns on,

598
00:28:32,040 --> 00:28:34,080
then maybe the picture
on your television

599
00:28:34,080 --> 00:28:36,240
shrinks because the
overall power delivered

600
00:28:36,240 --> 00:28:39,840
to all the other items
that you have in your house

601
00:28:39,840 --> 00:28:41,770
instantaneously drops.

602
00:28:41,770 --> 00:28:46,030
This is the kind of brownout
effect that you might have.

603
00:28:46,030 --> 00:28:47,610
You can have that on the chip.

604
00:28:47,610 --> 00:28:49,410
It is a very severe problem.

605
00:28:49,410 --> 00:28:52,200
It is one of the most
challenging problems

606
00:28:52,200 --> 00:28:54,780
to the designer of
the package system,

607
00:28:54,780 --> 00:28:57,340
to the designer of
computers, in fact.

608
00:28:57,340 --> 00:29:03,420
Usually the significant event
that causes power disturbs

609
00:29:03,420 --> 00:29:06,600
is simultaneous switching,
when a particular chip

610
00:29:06,600 --> 00:29:09,970
has to send a whole world of
information to another chip.

611
00:29:09,970 --> 00:29:13,620
That means all the off chip
drivers are switching together,

612
00:29:13,620 --> 00:29:17,430
that's the simultaneity factor.

613
00:29:17,430 --> 00:29:18,780
They all switch together.

614
00:29:18,780 --> 00:29:22,890
They all are suddenly demanding
additional power from the power

615
00:29:22,890 --> 00:29:25,830
supply, and if there are
substantial inductance

616
00:29:25,830 --> 00:29:28,290
in that power supply
connection, then the power

617
00:29:28,290 --> 00:29:30,790
will instantaneously
drop to the chip.

618
00:29:30,790 --> 00:29:34,230
This is the Delta I
problem, and it's once again

619
00:29:34,230 --> 00:29:36,870
related to the inductance of
that connection of the power

620
00:29:36,870 --> 00:29:38,790
to the chip through
the usual equation

621
00:29:38,790 --> 00:29:42,810
for inductive discontinuities.

622
00:29:42,810 --> 00:29:46,560
Here's a diagram to try and
illustrate how that happens.

623
00:29:46,560 --> 00:29:48,180
We have an active driver.

624
00:29:48,180 --> 00:29:50,490
It tries to send a
signal off the chip

625
00:29:50,490 --> 00:29:52,620
into that transmission line.

626
00:29:52,620 --> 00:29:56,250
As the active driver switches,
because of the inductance

627
00:29:56,250 --> 00:29:59,790
in that connection of the
power supply to plus V there,

628
00:29:59,790 --> 00:30:04,380
the power drops momentarily
to the active drivers.

629
00:30:04,380 --> 00:30:08,220
That has the effect of causing
some distortion on descent

630
00:30:08,220 --> 00:30:10,650
waveform from the active driver.

631
00:30:10,650 --> 00:30:13,530
It also has an effect
upon quiet circuits.

632
00:30:13,530 --> 00:30:15,480
Circuits that are not
actually switching

633
00:30:15,480 --> 00:30:17,340
at this point in time.

634
00:30:17,340 --> 00:30:21,210
You get disturbances propagated
out from quiet drivers,

635
00:30:21,210 --> 00:30:22,480
for example.

636
00:30:22,480 --> 00:30:26,550
And, so the active receiver
sees a distorted waveform.

637
00:30:26,550 --> 00:30:29,160
The quiet receiver
sees some distortion,

638
00:30:29,160 --> 00:30:31,710
which is sent to it,
because the quiet driver

639
00:30:31,710 --> 00:30:35,380
was disturbed through the
power supply connection.

640
00:30:35,380 --> 00:30:38,700
This is a significant challenge
as we go to high performance

641
00:30:38,700 --> 00:30:42,210
systems to worry about
these power disturbs

642
00:30:42,210 --> 00:30:45,300
and to minimize
these power disturbs.

643
00:30:45,300 --> 00:30:47,710
For the remainder of
this presentation,

644
00:30:47,710 --> 00:30:50,790
I'd like to look at the future
directions for packaging

645
00:30:50,790 --> 00:30:53,820
technology in particular
illustrate that with the work

646
00:30:53,820 --> 00:30:56,040
that we're doing MCC.

647
00:30:56,040 --> 00:30:59,130
And so let's start with a
picture on the puzzle box.

648
00:30:59,130 --> 00:31:02,290
What does a multi-chip
module look like?

649
00:31:02,290 --> 00:31:05,040
Here's an example of some work
that we've recently completed.

650
00:31:05,040 --> 00:31:07,860
It's a multi-chip module
approximately 2 and 1/2 inches

651
00:31:07,860 --> 00:31:11,190
square and contains 18 chips.

652
00:31:11,190 --> 00:31:16,290
It is a dual avionics
1750 A signal processor.

653
00:31:16,290 --> 00:31:20,100
That's nothing more to say
than it's really like a PC,

654
00:31:20,100 --> 00:31:24,570
but it's a PC that finds
its way into many pieces

655
00:31:24,570 --> 00:31:27,450
of military avionics.

656
00:31:27,450 --> 00:31:31,020
What you see here are
the bare chips attached

657
00:31:31,020 --> 00:31:33,000
to a high density interconnect.

658
00:31:33,000 --> 00:31:36,600
So instead of taking the chips,
putting it in a single chip

659
00:31:36,600 --> 00:31:39,150
package, and then connecting
those chips on a printed

660
00:31:39,150 --> 00:31:42,450
circuit board, what we do
now is we try and cluster

661
00:31:42,450 --> 00:31:46,590
as many chips as we possibly
can within, in this particular

662
00:31:46,590 --> 00:31:48,900
case, a 2 and 1/2
inch square box,

663
00:31:48,900 --> 00:31:51,360
and connect those chips
together, and only

664
00:31:51,360 --> 00:31:54,600
have a relatively
few number of I/O

665
00:31:54,600 --> 00:31:58,200
or interconnections out to the
next level of package, which

666
00:31:58,200 --> 00:32:01,260
typically could be, once
again, a printed circuit board,

667
00:32:01,260 --> 00:32:04,320
but, nonetheless, could be a far
simpler printed circuit board,

668
00:32:04,320 --> 00:32:06,450
than if we'd taken
these chips, put them

669
00:32:06,450 --> 00:32:09,450
in single chip packages,
and then connect those ships

670
00:32:09,450 --> 00:32:11,650
directly to the
printed circuit board.

671
00:32:11,650 --> 00:32:13,193
So this is the
kind of technology

672
00:32:13,193 --> 00:32:15,360
that I'm going to be talking
about for the remainder

673
00:32:15,360 --> 00:32:17,820
of this talk.

674
00:32:17,820 --> 00:32:20,280
What's our driving force
for the technologies

675
00:32:20,280 --> 00:32:22,730
that we're putting together?

676
00:32:22,730 --> 00:32:25,490
We've adopted a
superworkstation as a driving

677
00:32:25,490 --> 00:32:27,500
force for this work.

678
00:32:27,500 --> 00:32:31,100
We're looking at the future of
desktop computing if you will.

679
00:32:31,100 --> 00:32:35,360
What is the engineer going to
be using in the mid 1990's,

680
00:32:35,360 --> 00:32:38,810
or what is the engineer going
to be using by the year 2000?

681
00:32:38,810 --> 00:32:41,810
So let's consider what a
superworkstation for the 90's

682
00:32:41,810 --> 00:32:42,560
might look like.

683
00:32:42,560 --> 00:32:45,080


684
00:32:45,080 --> 00:32:49,410
One of the attributes is
it's going to be very fast.

685
00:32:49,410 --> 00:32:52,220
We have chosen a 3
nanosecond cycle time

686
00:32:52,220 --> 00:32:55,460
as the goal for our activity.

687
00:32:55,460 --> 00:32:58,160
3 nanosecond cycle time
means that this system

688
00:32:58,160 --> 00:33:00,710
will be running with
approximately a 300 megahertz

689
00:33:00,710 --> 00:33:02,160
clock.

690
00:33:02,160 --> 00:33:03,750
How big should the system be?

691
00:33:03,750 --> 00:33:05,670
One measure of
bigness of the system

692
00:33:05,670 --> 00:33:08,940
is, how many gates are
going to be in the CPU.

693
00:33:08,940 --> 00:33:12,420
We want to package 10
million gates within the CPU.

694
00:33:12,420 --> 00:33:15,100
10 million gates
is approximately 2,

695
00:33:15,100 --> 00:33:19,200
3, maybe 4 times larger
than present supercomputers.

696
00:33:19,200 --> 00:33:22,650
Whether it's a uni- or a
multi-processor I don't know.

697
00:33:22,650 --> 00:33:26,160
Let's just for the time being
consider a uni-processor

698
00:33:26,160 --> 00:33:30,330
of 10 million gates running
with a 3 nanosecond cycle time.

699
00:33:30,330 --> 00:33:32,820
One of the things that
we first need to consider

700
00:33:32,820 --> 00:33:35,100
is how does the
multi-chip module get us

701
00:33:35,100 --> 00:33:37,650
over that 50 megahertz barrier.

702
00:33:37,650 --> 00:33:39,660
Here's one view of
what the packaging

703
00:33:39,660 --> 00:33:41,550
technology of that
superworkstation

704
00:33:41,550 --> 00:33:42,690
would look like.

705
00:33:42,690 --> 00:33:46,830
I show 4 multi-chip modules
connected together in a stack.

706
00:33:46,830 --> 00:33:51,750
Each multi-chip module would
contain, let's say, 25 chips.

707
00:33:51,750 --> 00:33:53,220
Therefore, each
multi-chip module

708
00:33:53,220 --> 00:33:56,580
would contain maybe 2
and 1/2 million gates.

709
00:33:56,580 --> 00:33:58,950
Each module needs
to be removable,

710
00:33:58,950 --> 00:34:03,040
as I've shown with that third
module there being removed.

711
00:34:03,040 --> 00:34:06,150
There are connections that have
to run between the modules,

712
00:34:06,150 --> 00:34:08,580
and I show those connections
going through this side

713
00:34:08,580 --> 00:34:11,040
panels on either side.

714
00:34:11,040 --> 00:34:14,760
We have to work out how
we are going to power

715
00:34:14,760 --> 00:34:16,199
and cool these modules.

716
00:34:16,199 --> 00:34:18,960
And cooling is going to be
a significant challenge.

717
00:34:18,960 --> 00:34:21,659
I want to keep this
overall geometry

718
00:34:21,659 --> 00:34:24,300
of this cube of
computing here to be

719
00:34:24,300 --> 00:34:28,650
approximately 10 centimeters
high, 20 centimeters wide,

720
00:34:28,650 --> 00:34:30,030
and 10 centimeters deep.

721
00:34:30,030 --> 00:34:32,400
In other words, it's
a 1 liter volume

722
00:34:32,400 --> 00:34:34,590
that is the heart of the CPU.

723
00:34:34,590 --> 00:34:35,699
Why one liter?

724
00:34:35,699 --> 00:34:37,260
Because we have
to go back looking

725
00:34:37,260 --> 00:34:39,210
at that velocity of light.

726
00:34:39,210 --> 00:34:41,639
If I have 10
centimeters on this side

727
00:34:41,639 --> 00:34:44,130
to communicate anywhere
in this machine

728
00:34:44,130 --> 00:34:46,500
to anywhere else,
the maximum distance

729
00:34:46,500 --> 00:34:50,100
that I'll have to run with
Manhattan paths of avenues

730
00:34:50,100 --> 00:34:53,280
and streets and up and down
skyscrapers, if you will,

731
00:34:53,280 --> 00:34:55,679
is going to be 30 centimeters.

732
00:34:55,679 --> 00:34:57,480
And that's a maximum
distance I can

733
00:34:57,480 --> 00:35:02,610
go, considering the usual
velocity of signal propagation

734
00:35:02,610 --> 00:35:06,750
within computer systems
being approximately C upon 3.

735
00:35:06,750 --> 00:35:10,350
Let's look at what multi-chip
modules are in existence,

736
00:35:10,350 --> 00:35:12,250
at the present moment.

737
00:35:12,250 --> 00:35:14,250
The first to introduce
multi-chip modules

738
00:35:14,250 --> 00:35:17,460
were the mainframe and
supercomputer manufacturers,

739
00:35:17,460 --> 00:35:19,710
and IBM is a very good example.

740
00:35:19,710 --> 00:35:23,310
Back in the early
1980's, IBM introduced

741
00:35:23,310 --> 00:35:26,100
their TCM, their thermal
conduction module.

742
00:35:26,100 --> 00:35:30,120
It was a multi-chip module based
on building the interconnect

743
00:35:30,120 --> 00:35:34,470
in a monolithic slab of alumina
with molybdenum interconnect.

744
00:35:34,470 --> 00:35:37,740
And it was really made up
of lots of ceramic layers

745
00:35:37,740 --> 00:35:39,990
laminated together.

746
00:35:39,990 --> 00:35:43,260
The actual interconnect itself
had a characteristic impedance

747
00:35:43,260 --> 00:35:47,530
of approximately 55 ohms
and yet on the other hand,

748
00:35:47,530 --> 00:35:50,550
it was quite resistive because
they were using molybdenum.

749
00:35:50,550 --> 00:35:53,580
They connected the chips
by putting solder balls

750
00:35:53,580 --> 00:35:56,970
on the chips and flipping
them, and reflowing that solder

751
00:35:56,970 --> 00:35:58,770
to connect the
chips to the surface

752
00:35:58,770 --> 00:36:01,860
of the monolithic
alumina substrate.

753
00:36:01,860 --> 00:36:04,590
Cooling was done
with pistons that

754
00:36:04,590 --> 00:36:07,950
rested on the back of the chips
to conduct the heat to a water

755
00:36:07,950 --> 00:36:09,090
jacket.

756
00:36:09,090 --> 00:36:12,150
One of the concerns is the
TCE, the thermal coefficient

757
00:36:12,150 --> 00:36:15,690
of expansion, of the different
materials that are used

758
00:36:15,690 --> 00:36:18,270
within the packaging structure.

759
00:36:18,270 --> 00:36:20,130
On the one hand,
we have silicon,

760
00:36:20,130 --> 00:36:22,860
the silicon of the
chips, which expands

761
00:36:22,860 --> 00:36:26,010
at approximately 3
ppm per degrees C.

762
00:36:26,010 --> 00:36:29,070
And, then on the other hand, you
have the package with alumina

763
00:36:29,070 --> 00:36:32,370
which is 7 ppm, and
the moly within that,

764
00:36:32,370 --> 00:36:36,300
the moly for the actual
conductors, which is 5 ppm.

765
00:36:36,300 --> 00:36:39,180
So as the system heats
up and cools down,

766
00:36:39,180 --> 00:36:43,140
various portions of the
system shrink or enlarge

767
00:36:43,140 --> 00:36:44,650
at different amounts.

768
00:36:44,650 --> 00:36:46,860
And this is a
significant challenge

769
00:36:46,860 --> 00:36:49,290
to work with, to
ensure that there

770
00:36:49,290 --> 00:36:52,710
are no reliability
problems with the shrinking

771
00:36:52,710 --> 00:36:55,830
and expansion of various
parts of the system as you

772
00:36:55,830 --> 00:36:59,430
go through the operation
and use of these systems.

773
00:36:59,430 --> 00:37:01,200
The solution to
multi-chip modules

774
00:37:01,200 --> 00:37:04,110
that IBM adopted in
the early 1980's is

775
00:37:04,110 --> 00:37:06,090
shown diagrammatically here.

776
00:37:06,090 --> 00:37:08,610
The chips are connected
to the alumina substrate

777
00:37:08,610 --> 00:37:12,000
through their solder ball
technology, called C4.

778
00:37:12,000 --> 00:37:14,520
The heat is removed from
the chips by conduction

779
00:37:14,520 --> 00:37:17,640
through the pistons through
the hat to the cold plate.

780
00:37:17,640 --> 00:37:20,250
And the cold plate is
kept cool by actually

781
00:37:20,250 --> 00:37:25,020
flowing chilled water through
channels in that plate.

782
00:37:25,020 --> 00:37:27,390
This is the approach
that IBM took.

783
00:37:27,390 --> 00:37:30,300
It turns out that it is
a very expensive approach

784
00:37:30,300 --> 00:37:32,520
to the building of the
multi-chip modules.

785
00:37:32,520 --> 00:37:34,770
It's not too expensive
that you cannot use it

786
00:37:34,770 --> 00:37:37,470
in a supercomputer
or a large mainframe,

787
00:37:37,470 --> 00:37:40,050
but it's certainly much
more expensive than the kind

788
00:37:40,050 --> 00:37:43,620
of technology that you'd want to
put in that simple workstation

789
00:37:43,620 --> 00:37:48,810
of the 1990's, or eventually
into a PC of the year 2000.

790
00:37:48,810 --> 00:37:53,940
So let's look at the
requirements that we might have

791
00:37:53,940 --> 00:37:56,820
on the cost of the packaging
technology for that

792
00:37:56,820 --> 00:38:00,240
superworkstation of the 1990's.

793
00:38:00,240 --> 00:38:02,250
Typically in that
time we'll expect

794
00:38:02,250 --> 00:38:06,220
that chips are going
to cost maybe $25 each.

795
00:38:06,220 --> 00:38:08,970
So with 100 chips
in that system,

796
00:38:08,970 --> 00:38:14,310
$2,500 is going to go into
the cost of the chips.

797
00:38:14,310 --> 00:38:17,550
Now I estimate that the
packaging technology

798
00:38:17,550 --> 00:38:22,140
must account for no more
than maybe $1,200 or $1,500

799
00:38:22,140 --> 00:38:24,540
in addition to the
cost of those chips.

800
00:38:24,540 --> 00:38:29,100
So I've presently budgeted
here $1,200 for the packaging

801
00:38:29,100 --> 00:38:31,050
into those four
multi-chip modules

802
00:38:31,050 --> 00:38:34,260
that I had in the diagram
of the stacked modules.

803
00:38:34,260 --> 00:38:37,710
Maybe an additional $300 for
the connectors and the printed

804
00:38:37,710 --> 00:38:42,140
circuit board that these modules
may be communicating with.

805
00:38:42,140 --> 00:38:44,570
And then maybe
another $1,000 need

806
00:38:44,570 --> 00:38:47,540
to be budgeted for how we're
going to test this system,

807
00:38:47,540 --> 00:38:50,540
for the functional test of
the components like the chips,

808
00:38:50,540 --> 00:38:52,820
the subassemblies, like
the multi-chip modules,

809
00:38:52,820 --> 00:38:54,960
and for the complete system.

810
00:38:54,960 --> 00:38:57,350
So the cost breakdown
of our superworkstation

811
00:38:57,350 --> 00:38:59,240
would look something like this.

812
00:38:59,240 --> 00:39:01,790
1/2 of the cost is going
to go in the chips.

813
00:39:01,790 --> 00:39:04,400
A 1/4 of the cost is going
to go in the package.

814
00:39:04,400 --> 00:39:07,720
And the remainder is going
to be in the testing.

815
00:39:07,720 --> 00:39:10,860
So we have something
like a $5,000 cost

816
00:39:10,860 --> 00:39:13,650
for this superworkstation.

817
00:39:13,650 --> 00:39:17,040
So what are the
challenges to this system?

818
00:39:17,040 --> 00:39:20,160
I put a lot of
emphasis on cost, and I

819
00:39:20,160 --> 00:39:21,660
think that's an
important message

820
00:39:21,660 --> 00:39:23,410
that I want to get across.

821
00:39:23,410 --> 00:39:26,880
There is always, generally
speaking in this area,

822
00:39:26,880 --> 00:39:31,120
you can always find a technical
solution to a problem.

823
00:39:31,120 --> 00:39:33,520
It turns out that many
technical solutions.

824
00:39:33,520 --> 00:39:38,330
Our far too costly, and it
is the low cost solutions

825
00:39:38,330 --> 00:39:40,830
that are going to be the
effective solutions, that

826
00:39:40,830 --> 00:39:43,930
are finally going to find
their way to the marketplace.

827
00:39:43,930 --> 00:39:47,820
So it's very easy to get
blinded by great technology.

828
00:39:47,820 --> 00:39:51,520
You can lose sight
of the market needs.

829
00:39:51,520 --> 00:39:55,270
You've got to focus on cost and
that is really the challenge

830
00:39:55,270 --> 00:39:58,900
that we're trying to tackle
at MCC at the present moment.

831
00:39:58,900 --> 00:40:01,810
And let me give you some
examples of the technology

832
00:40:01,810 --> 00:40:04,990
and where those
cost and performance

833
00:40:04,990 --> 00:40:07,000
requirements come to play.

834
00:40:07,000 --> 00:40:10,510
For the interconnect between the
chips in the multi-chip module,

835
00:40:10,510 --> 00:40:14,680
we've chosen an approach which
uses copper and polyimide.

836
00:40:14,680 --> 00:40:19,720
So that's the acronym at the top
there, CuPI, copper polyimide.

837
00:40:19,720 --> 00:40:24,820
And we've adopted an approach
that we believe will ultimately

838
00:40:24,820 --> 00:40:28,390
lead to a very low
cost manufacturing

839
00:40:28,390 --> 00:40:29,950
of the high density
of interconnect,

840
00:40:29,950 --> 00:40:32,170
that is needed to run
the communications

841
00:40:32,170 --> 00:40:33,670
between the chips.

842
00:40:33,670 --> 00:40:36,340
We're taking an approach
of plating for making up

843
00:40:36,340 --> 00:40:38,080
the copper layers.

844
00:40:38,080 --> 00:40:41,020
We're taking an approach
of very simply polishing,

845
00:40:41,020 --> 00:40:42,880
for planarizing the structures.

846
00:40:42,880 --> 00:40:45,040
As you build up
multilayered structures,

847
00:40:45,040 --> 00:40:47,440
they can very easily
and very rapidly

848
00:40:47,440 --> 00:40:49,750
get out of being planar.

849
00:40:49,750 --> 00:40:54,460
Because of the patterning of the
structures that you're making,

850
00:40:54,460 --> 00:40:58,090
you end up with
non-planar structures,

851
00:40:58,090 --> 00:40:59,300
if you're not careful.

852
00:40:59,300 --> 00:41:02,110
And so, we've adopted
the approach of polishing

853
00:41:02,110 --> 00:41:04,840
for achieving the planarization.

854
00:41:04,840 --> 00:41:07,000
We're typically
making conductors

855
00:41:07,000 --> 00:41:12,460
that are 5 microns thick
and maybe 15 microns wide.

856
00:41:12,460 --> 00:41:14,890
Similarly the
insulator, the polyimide

857
00:41:14,890 --> 00:41:19,448
in this particular case, is of
the order of 15 microns thick.

858
00:41:19,448 --> 00:41:21,490
With the kinds of structures
that we're building,

859
00:41:21,490 --> 00:41:24,580
then, we end up with
transmission lines

860
00:41:24,580 --> 00:41:27,010
used for communicating
between the chips.

861
00:41:27,010 --> 00:41:29,590
Transmission lines that have
a characteristic impedance

862
00:41:29,590 --> 00:41:31,020
in the range of 50 ohms.

863
00:41:31,020 --> 00:41:34,810
It can be as low as 40, it
can be as high as 70 or 80.

864
00:41:34,810 --> 00:41:36,880
It depends on what
you want to do as far

865
00:41:36,880 --> 00:41:38,860
as how you want to design it.

866
00:41:38,860 --> 00:41:40,480
We find that this
kind of structure

867
00:41:40,480 --> 00:41:43,270
is very suitable for passing
signals with risetimes

868
00:41:43,270 --> 00:41:45,785
of less than 200 picoseconds.

869
00:41:45,785 --> 00:41:47,410
The bottom of the
slide I've introduced

870
00:41:47,410 --> 00:41:51,100
a new parameter, that of
the thermal performance

871
00:41:51,100 --> 00:41:52,640
of the package.

872
00:41:52,640 --> 00:41:54,910
We want to try and achieve
less than 1/2 a degree

873
00:41:54,910 --> 00:41:58,570
C per watt per square centimeter
for the cooling of the chips

874
00:41:58,570 --> 00:42:00,850
for the thermal path
between the chip

875
00:42:00,850 --> 00:42:02,920
and where we've
put the heat sink.

876
00:42:02,920 --> 00:42:05,440
That means that a 10
watt chip 1 square

877
00:42:05,440 --> 00:42:08,290
centimeter would be
no more than 5 degrees

878
00:42:08,290 --> 00:42:12,820
centigrade above the
temperature of the heat sink.

879
00:42:12,820 --> 00:42:16,570
Here's an example of the
copper polyimide technology

880
00:42:16,570 --> 00:42:19,210
that we're making at MCC.

881
00:42:19,210 --> 00:42:22,150
First what you see, this
is a section through it.

882
00:42:22,150 --> 00:42:25,450
What you see at the very
bottom is the rough surface

883
00:42:25,450 --> 00:42:27,610
of the substrate on
which this is made.

884
00:42:27,610 --> 00:42:29,650
We're typically
working with alumina.

885
00:42:29,650 --> 00:42:30,790
We could use silicon.

886
00:42:30,790 --> 00:42:33,460
We could actually use a metal.

887
00:42:33,460 --> 00:42:37,252
What we build up are then,
on top of that substrate,

888
00:42:37,252 --> 00:42:38,710
are the layers that
are going to be

889
00:42:38,710 --> 00:42:42,100
used for the interconnect
between the chips.

890
00:42:42,100 --> 00:42:45,820
In this particular case, we've
got 5 layers of interconnect.

891
00:42:45,820 --> 00:42:49,160
We can call them x
y, power and ground.

892
00:42:49,160 --> 00:42:51,850
And then on top, we
have the bond pad layer

893
00:42:51,850 --> 00:42:55,420
where the chip connections
are going to be connected to.

894
00:42:55,420 --> 00:42:58,240
This is a kind of technology
that we're building.

895
00:42:58,240 --> 00:43:00,840
The line widths that you
see there to the right

896
00:43:00,840 --> 00:43:06,400
are of the order of 10 microns
wide with a 10 micron spacing,

897
00:43:06,400 --> 00:43:09,490
and they're about
5 microns thick.

898
00:43:09,490 --> 00:43:12,310
These lines in this
particular case

899
00:43:12,310 --> 00:43:15,800
being only 10 microns
apart are really too close.

900
00:43:15,800 --> 00:43:18,950
And if you run those lines
for too long a distance,

901
00:43:18,950 --> 00:43:21,910
then you get into really
significant difficulties

902
00:43:21,910 --> 00:43:24,435
with regards to crosstalk,
the backward wave

903
00:43:24,435 --> 00:43:25,810
and the forward
wave of crosstalk

904
00:43:25,810 --> 00:43:27,730
that we've been talking about.

905
00:43:27,730 --> 00:43:29,740
So, although in this
particular diagram

906
00:43:29,740 --> 00:43:32,920
I show 10 micron lines
with 10 micron spaces,

907
00:43:32,920 --> 00:43:36,070
we find that it is far more
desirable to have something

908
00:43:36,070 --> 00:43:40,900
like a 15 micron line
and maybe a 30 micron

909
00:43:40,900 --> 00:43:44,120
space between those lines.

910
00:43:44,120 --> 00:43:46,120
The other important
feature about this

911
00:43:46,120 --> 00:43:50,170
is that you're able, with
the plating technology,

912
00:43:50,170 --> 00:43:53,680
to plate up the conductor,
the copper, to connect

913
00:43:53,680 --> 00:43:56,890
between these layers,
these five metal layers.

914
00:43:56,890 --> 00:43:59,170
You can plate that
copper up vertically,

915
00:43:59,170 --> 00:44:02,050
as is shown right down the
middle of the slide, that

916
00:44:02,050 --> 00:44:05,590
makes a very low
thermal impedance

917
00:44:05,590 --> 00:44:08,170
path between the chip, which
is going to be attached

918
00:44:08,170 --> 00:44:10,420
to the top of this
slide and the base,

919
00:44:10,420 --> 00:44:12,220
the substrate,
which is the alumina

920
00:44:12,220 --> 00:44:13,900
at the bottom of this slide.

921
00:44:13,900 --> 00:44:16,870
There is a very
efficient thermal path

922
00:44:16,870 --> 00:44:20,260
from the chip to where the
heat sink is going to be.

923
00:44:20,260 --> 00:44:23,260
And it's necessary to use
that copper in that fashion

924
00:44:23,260 --> 00:44:26,420
to get that good
thermal performance.

925
00:44:26,420 --> 00:44:30,230
We are developing TAB technology
for connecting the chips

926
00:44:30,230 --> 00:44:31,700
to the high density
interconnect.

927
00:44:31,700 --> 00:44:35,180
TAB is, if you remember
tape automated bonding.

928
00:44:35,180 --> 00:44:38,090
And in this particular
case, you take chips

929
00:44:38,090 --> 00:44:40,340
and connect them
to a 35 millimeter

930
00:44:40,340 --> 00:44:43,280
format of copper conductors.

931
00:44:43,280 --> 00:44:45,380
The chips are connected
through a process

932
00:44:45,380 --> 00:44:46,820
of inner lead bonding.

933
00:44:46,820 --> 00:44:49,130
And that can be done with
all the needs at once,

934
00:44:49,130 --> 00:44:52,750
or it can be done on
the lead by lead basis.

935
00:44:52,750 --> 00:44:57,600
MCC has developed a method of
laser bonding of these chips.

936
00:44:57,600 --> 00:45:00,320


937
00:45:00,320 --> 00:45:04,130
Here's an example of a chip
connected to a TAB lead frame,

938
00:45:04,130 --> 00:45:06,320
a tape automated
bounded lead frame.

939
00:45:06,320 --> 00:45:09,900
What you see here are the leads
that connect to the chips.

940
00:45:09,900 --> 00:45:11,750
They're actually a
silvery color that

941
00:45:11,750 --> 00:45:14,720
is a tin plated copper lead
that is connected to the chip.

942
00:45:14,720 --> 00:45:19,760


943
00:45:19,760 --> 00:45:24,980
The next stage is to take and
cut the leads and the chip away

944
00:45:24,980 --> 00:45:27,230
from the tape
frame, and then bond

945
00:45:27,230 --> 00:45:29,300
them to the high
density interconnect.

946
00:45:29,300 --> 00:45:34,940
And this is a view of some
chips or, the more precisely,

947
00:45:34,940 --> 00:45:38,690
the corners of chips that have
been connected to high density

948
00:45:38,690 --> 00:45:40,080
interconnect.

949
00:45:40,080 --> 00:45:43,100
You see the very
fine connections that

950
00:45:43,100 --> 00:45:45,050
are made between the chips.

951
00:45:45,050 --> 00:45:48,950
The bars that are resting
on top of those connections

952
00:45:48,950 --> 00:45:51,410
are actually polyimide
stiffening rings

953
00:45:51,410 --> 00:45:53,870
to hold the leads in place
before the connections

954
00:45:53,870 --> 00:45:55,160
are made.

955
00:45:55,160 --> 00:45:58,310
So from the top of the
chip, the leads run out,

956
00:45:58,310 --> 00:45:59,990
they are bent
down, and then they

957
00:45:59,990 --> 00:46:02,810
are connected to the top
surface of the interconnect.

958
00:46:02,810 --> 00:46:05,780
In this particular
example, the leads

959
00:46:05,780 --> 00:46:08,930
are spaced where they make
connection to the high density

960
00:46:08,930 --> 00:46:09,770
interconnect.

961
00:46:09,770 --> 00:46:13,760
The leads of space at
approximately 10 mils.

962
00:46:13,760 --> 00:46:16,980
Now let's look at
the cooling problems.

963
00:46:16,980 --> 00:46:20,070
Now, one of the first things
that we needed to decide

964
00:46:20,070 --> 00:46:24,480
is we were thinking about this
superworkstation of the 1990's,

965
00:46:24,480 --> 00:46:27,330
is whether we would take an
approach of liquid cooling,

966
00:46:27,330 --> 00:46:30,060
or whether we could do
it with air cooling.

967
00:46:30,060 --> 00:46:34,350
Now, if you remember, I
mentioned in the IBM TCM.

968
00:46:34,350 --> 00:46:39,360
They had a way of conducting
the heat to a water cool plate.

969
00:46:39,360 --> 00:46:43,050
Now, you can certainly remove
the large amounts of heat

970
00:46:43,050 --> 00:46:47,430
that you can expect from
the vintage 95 chips.

971
00:46:47,430 --> 00:46:51,660
And you can improve the cooling
efficiency of that cold plate

972
00:46:51,660 --> 00:46:55,560
through such things as
using microchannels.

973
00:46:55,560 --> 00:46:58,020
What we have devised
at MCC, though,

974
00:46:58,020 --> 00:47:00,630
is a way of making
microchannels for air,

975
00:47:00,630 --> 00:47:04,080
efficient ways of dumping
the heat from the chip

976
00:47:04,080 --> 00:47:06,130
into the air.

977
00:47:06,130 --> 00:47:09,400
What we've developed is
a air cooling technology

978
00:47:09,400 --> 00:47:11,080
called Zephyr technology.

979
00:47:11,080 --> 00:47:13,810
But let's look at the
liquid cooling technology

980
00:47:13,810 --> 00:47:16,690
upon which it's based.

981
00:47:16,690 --> 00:47:21,010
In this particular case, we
show a very high enlargement

982
00:47:21,010 --> 00:47:23,440
of channels that are
cut into silicon.

983
00:47:23,440 --> 00:47:29,350
Each of these channels are
maybe 40, 50, or 60 microns wide

984
00:47:29,350 --> 00:47:32,020
and maybe 200 or
300 microns deep.

985
00:47:32,020 --> 00:47:34,600
If you flow water through
these narrow channels

986
00:47:34,600 --> 00:47:36,760
you can remove substantial
amounts of heat

987
00:47:36,760 --> 00:47:37,990
from the silicon.

988
00:47:37,990 --> 00:47:42,220
This work was done in the early
1980's by Tuckerman and Pease

989
00:47:42,220 --> 00:47:44,440
at Stanford.

990
00:47:44,440 --> 00:47:49,630
This is a very efficient way of
removing heat from the silicon.

991
00:47:49,630 --> 00:47:51,910
The water stays in
the laminar flow

992
00:47:51,910 --> 00:47:54,160
as it flows through
these channels.

993
00:47:54,160 --> 00:47:58,060
There's no turbulence or
insignificant turbulence.

994
00:47:58,060 --> 00:48:00,910
It's a very efficient
way of removing heat.

995
00:48:00,910 --> 00:48:03,845
What we've done is we've
taken these kinds of concepts,

996
00:48:03,845 --> 00:48:07,360
and we've applied it to
our cooling technology.

997
00:48:07,360 --> 00:48:09,550
In this particular
case, it shows a number

998
00:48:09,550 --> 00:48:12,760
of heat sinks, which are
air cooling heat sinks,

999
00:48:12,760 --> 00:48:15,250
where we use some of
the same principles.

1000
00:48:15,250 --> 00:48:17,530
We passed the air
through these heat sinks.

1001
00:48:17,530 --> 00:48:19,690
We keep the air as
much as we possibly

1002
00:48:19,690 --> 00:48:22,390
can in laminar
flow, that is most

1003
00:48:22,390 --> 00:48:24,850
efficient from the point
of view of transferring

1004
00:48:24,850 --> 00:48:27,160
the heat between the
heat sink in the air,

1005
00:48:27,160 --> 00:48:29,260
and is also very
important at being

1006
00:48:29,260 --> 00:48:33,460
able to keep down the noise
of the cooling of the air.

1007
00:48:33,460 --> 00:48:35,560
One of the big problems
with air cooling

1008
00:48:35,560 --> 00:48:37,810
is, as you push the
air faster and faster,

1009
00:48:37,810 --> 00:48:42,070
you get into problems
with vortices

1010
00:48:42,070 --> 00:48:46,090
and with non-laminar flow,
and it becomes very noisy.

1011
00:48:46,090 --> 00:48:49,875
It requires a higher pressure
head to push that air through.

1012
00:48:49,875 --> 00:48:52,172
It becomes a very
inefficient system.

1013
00:48:52,172 --> 00:48:54,130
What we've been able to
do here with these heat

1014
00:48:54,130 --> 00:48:57,610
sinks is to keep that
air in laminar flow

1015
00:48:57,610 --> 00:49:00,460
and working very
efficiently for us.

1016
00:49:00,460 --> 00:49:02,350
Here's a further example.

1017
00:49:02,350 --> 00:49:04,900
You see the very fine
channels that the air

1018
00:49:04,900 --> 00:49:06,280
has to flow through.

1019
00:49:06,280 --> 00:49:08,500
The air actually
enters in the center

1020
00:49:08,500 --> 00:49:12,460
and flows out down the
two diagonal sides lower

1021
00:49:12,460 --> 00:49:15,590
in the picture.

1022
00:49:15,590 --> 00:49:18,560
We have been able to show
that with this technology

1023
00:49:18,560 --> 00:49:20,870
that the supercomputer
that we're talking about,

1024
00:49:20,870 --> 00:49:24,830
the superworkstation, can
actually be air cooled.

1025
00:49:24,830 --> 00:49:29,405
We've shown that we can achieve
less than 1.5 Kelvins per watt

1026
00:49:29,405 --> 00:49:31,550
per square centimeter
of cooling performance

1027
00:49:31,550 --> 00:49:35,060
with this kind of technology,
with very low acoustic noise,

1028
00:49:35,060 --> 00:49:36,590
less than 50 dBA.

1029
00:49:36,590 --> 00:49:38,490
That means that it is adequate.

1030
00:49:38,490 --> 00:49:42,060
It is suitable for putting
in an office environment.

1031
00:49:42,060 --> 00:49:45,800
So we think the air cooling can
remove the amounts of heat that

1032
00:49:45,800 --> 00:49:48,440
we will have in our
supercomputer of the mid

1033
00:49:48,440 --> 00:49:49,760
1990's.

1034
00:49:49,760 --> 00:49:52,340
And one of the
challenges now is to get

1035
00:49:52,340 --> 00:49:55,550
that connection,
thermal connection,

1036
00:49:55,550 --> 00:49:57,980
between the chip
and the heat sink.

1037
00:49:57,980 --> 00:50:00,260
Now I've already
talked about the fact

1038
00:50:00,260 --> 00:50:02,270
that with our copper
polyimide technology

1039
00:50:02,270 --> 00:50:05,930
we can put thermal veirs
vertical copper conducting

1040
00:50:05,930 --> 00:50:09,980
paths from the chip
through the interconnect.

1041
00:50:09,980 --> 00:50:13,970
And these thermal paths together
with the high performance

1042
00:50:13,970 --> 00:50:17,090
of the air cooling will
satisfy our requirements

1043
00:50:17,090 --> 00:50:22,130
with this superworkstation
of the 1995 time frame.

1044
00:50:22,130 --> 00:50:24,080
With the new
technologies associated

1045
00:50:24,080 --> 00:50:27,590
with multi-chip modules, it
is important to also look

1046
00:50:27,590 --> 00:50:31,010
for a breakthrough in
the time to market.

1047
00:50:31,010 --> 00:50:33,290
Time to market becomes
extremely important.

1048
00:50:33,290 --> 00:50:35,300
Design iterations at
the present moment

1049
00:50:35,300 --> 00:50:38,310
can take far too
long, over a year.

1050
00:50:38,310 --> 00:50:41,120
We need a way of fast
prototyping hardware.

1051
00:50:41,120 --> 00:50:45,530
We need a way of rapidly getting
new designs into manufacturing,

1052
00:50:45,530 --> 00:50:48,080
because rapid
demonstration of capability

1053
00:50:48,080 --> 00:50:50,510
wins contracts and customers.

1054
00:50:50,510 --> 00:50:53,540
We have developed at MCC
one way of doing this

1055
00:50:53,540 --> 00:50:55,970
with something that we
call quick turnaround

1056
00:50:55,970 --> 00:50:56,870
interconnect, QTAI.

1057
00:50:56,870 --> 00:50:59,660


1058
00:50:59,660 --> 00:51:04,430
Rather than defining each
level in the structure

1059
00:51:04,430 --> 00:51:08,300
of the interconnect, we
predefined power, ground, x

1060
00:51:08,300 --> 00:51:09,670
and y signals.

1061
00:51:09,670 --> 00:51:12,200
Such that they are the
same for all applications.

1062
00:51:12,200 --> 00:51:14,420
And what we do is
we just personalize

1063
00:51:14,420 --> 00:51:18,320
for a specific application by
putting links on the surface

1064
00:51:18,320 --> 00:51:20,090
and defining where
the paths are,

1065
00:51:20,090 --> 00:51:22,380
as is shown in the next slide.

1066
00:51:22,380 --> 00:51:26,060
So what we have with
the dielectric layers

1067
00:51:26,060 --> 00:51:29,750
and the buried wire segments
is an unpersonalized array

1068
00:51:29,750 --> 00:51:31,400
of interconnect,
which we can now

1069
00:51:31,400 --> 00:51:34,100
personalize with surface links.

1070
00:51:34,100 --> 00:51:38,340
We can do that personalization
in only a matter of a few days.

1071
00:51:38,340 --> 00:51:41,270
So with the personalization
of a few days,

1072
00:51:41,270 --> 00:51:44,090
you can then assemble the
chips onto this interconnect

1073
00:51:44,090 --> 00:51:48,180
and be testing a new
prototype within a week.

1074
00:51:48,180 --> 00:51:51,260
So this gives us a way of
very rapidly prototyping

1075
00:51:51,260 --> 00:51:53,990
new designs.

1076
00:51:53,990 --> 00:51:57,020
This particular design
was built in that fashion.

1077
00:51:57,020 --> 00:52:00,980
We have built an early version
of our array of interconnect,

1078
00:52:00,980 --> 00:52:02,420
our QTAI.

1079
00:52:02,420 --> 00:52:05,780
We have then routed
and designed where

1080
00:52:05,780 --> 00:52:09,290
the links need to go to connect
all the x segments and the y

1081
00:52:09,290 --> 00:52:11,990
segments to connect
between these chips.

1082
00:52:11,990 --> 00:52:16,280
In this particular case, we
have connected 16 VLSI chips

1083
00:52:16,280 --> 00:52:20,240
onto the top surface
of QTAI interconnect.

1084
00:52:20,240 --> 00:52:22,040
This particular
multi-chip module

1085
00:52:22,040 --> 00:52:26,120
is once again approximately
2 and 1/4 inches square.

1086
00:52:26,120 --> 00:52:29,840
This is the kind of approach
that we believe is necessary

1087
00:52:29,840 --> 00:52:35,780
to get quick prototyping as well
as rapid entry into production

1088
00:52:35,780 --> 00:52:39,740
of new technologies, of
advanced technologies,

1089
00:52:39,740 --> 00:52:41,930
technologies that are
going to be appropriate

1090
00:52:41,930 --> 00:52:47,190
for the superworkstation
of the 1990's.

1091
00:52:47,190 --> 00:52:50,000
So with this, I would
like to conclude.

1092
00:52:50,000 --> 00:52:54,080
In the 80's, we have seen rapid
advances in chip technology

1093
00:52:54,080 --> 00:52:56,420
and maybe less in
packaging technology.

1094
00:52:56,420 --> 00:52:57,950
As we move into
the 90's, there are

1095
00:52:57,950 --> 00:53:01,400
going to continue to be rapid
advances in the chip technology

1096
00:53:01,400 --> 00:53:05,030
and the package technology
has to catch up.

1097
00:53:05,030 --> 00:53:08,360
We believe that the main
approach in the packaging arena

1098
00:53:08,360 --> 00:53:11,240
is going to be with
multi-chip modules.

1099
00:53:11,240 --> 00:53:13,400
I do believe that
multi-chip modules will

1100
00:53:13,400 --> 00:53:18,750
be used in workstations and
PCs by the end of this decade.

1101
00:53:18,750 --> 00:53:20,420
So what we've got
to do is we've got

1102
00:53:20,420 --> 00:53:22,520
to work out how to
dramatically reduce

1103
00:53:22,520 --> 00:53:25,070
the cost of multi-chip modules.

1104
00:53:25,070 --> 00:53:28,280
It all seems to be possible with
today's knowledge of materials

1105
00:53:28,280 --> 00:53:29,600
and manufacturing.

1106
00:53:29,600 --> 00:53:32,480
All that remains to
be done is to do it.

1107
00:53:32,480 --> 00:53:33,380
Thank you.

1108
00:53:33,380 --> 00:53:35,530
[MUSIC PLAYING]

1109
00:53:35,530 --> 00:55:33,000