[MUSIC PLAYING]
SPEAKER 1: University Video Communications,
with the sponsorship of MCC, welcomes you
to this edition of the Distinguished Lecture Series;
Leaders in Computer Science and Electrical Engineering.
Dennis Herrell, Vise President and program director
of MCC's Semiconductor Packaging and Interconnect Program,
joined MCC in 1985 after a distinguished 21 year
career at IBM.
He has a BS in physics from Imperial College of Science
and Technology London and a PhD in physics
from Cambridge University.
In this lecture, Dr Herrell sets the technical and economic
goals for advanced packaging, making the point
that future chip development is dependent upon the development
of packaging technology.
He outlines the critical considerations
for packaging design in the 90's, illustrating his talk
with MCC developments like the multi-chip module.
Dennis Herrell.
DENNIS HERRELL: Packaging and interconnect technology
has been one of the areas of most exciting work
in the recent years.
Chips need to be connected into systems,
and this is the area that packaging and interconnect
tries to cover.
Chip technology has been improving dramatically through
the 1980's, and that improvement is going to continue through
the 1990's.
We're going to move to finer and finer
line technologies of the chip.
We're presently working in the domain
of maybe 1 micron, 0.8 micron, through the line
widths on these chips.
And we're going to get to much smaller line widths
as we go through the 1990's, so that we're
down to maybe 1/3 of the micron by the time we get to the year
2000.
Larger chips will be coming along.
At the present moment, chips are only less
than a centimeter on this side.
They're going to be 2 or maybe even 3 centimeters by the year
2000.
So that is where chip technology is going to take us.
And the packaging technology has to keep pace
with that rapid demand--
that rapid improvement in the chip technology.
What we really also need to understand
is where the computer technology is
going to go in the 1990's, because we, on the one hand,
know where the chip is going to go,
but we really have to understand where
the computers are going to go.
Because the packaging and interconnect technology really
produces the bridge between the chip, on the one hand,
and how you put them in the computer, on the other hand.
Processing performance demands are
going to continue to increase.
People are going to want to have more
storage on their computers.
They're going to want fast interactive systems.
There's going to be more and more demand for animation.
There's going to be more and more demand for speech
processing; computers that can recognize your speech,
computers that can speak back to you.
And there's going to be more and more stress
on the accessing of large pieces of information,
large databases.
So there's going to be a lot of effort in the area of storage
and networking as we go through the 90's
and into the new century.
So we really want to look now at what advances are
needed in the packaging area.
So we talked about larger chips.
They're going to be faster.
They're going to be more power hungry.
Now it turned out in the 1980's that with the rapid improvement
in the chip technology the packaging technology really
took a backseat.
Everybody and their uncle working on chips
and the packaging technology people were kind of
relegated to the back room, and as soon
as the chips came out of the door
they're expected to package them.
And that rapid development and chip technologies and designs
is going to continue through the 1990's, but people are now
beginning to wake up to the fact that system performance is not
just achieved by making better chips.
You have to keep the packaging technology in step
with the improvements that are happening in the chips.
Here's an example of what's happened in the past.
We started out with systems, or chips,
which maybe were made with 10 micron lithography technology.
With systems that are made with chips like that,
maybe the clock frequency was only as high as 1 megahertz,
and the overall portion of the cycle that
was involved with the packaging delays,
or the overall power that the packaging used up
in that system, was only maybe about 10% or 15%
of the overall system.
But as we're now moving to 1/2 micron technology,
and we're looking at systems that
might be running as fast as 100 megahertz,
we've got to contemplate that the packaging is going
to take up maybe 1/2 or even larger
portion of both the power and the delay within the system.
And this is the challenge that the packaging engineer now
has to try and see what new innovations he can bring
that is going to make the package component
delays and the package power portion still, for example,
keep it below 50%.
So with these things in mind, let's overview
some of the driving forces behind the things
that we have to do in the packaging arena.
I've talked about the chip.
Let's go back and think a little bit more about that chip.
Some people call it the integrated circuit.
Most of the chips out there at the present moment
a silicon technology chips.
We hear of acronyms like CMOS, Bipolar, BICMOS.
These are the standard chip technologies
that we have at the present moment.
They're dramatically improving in performance.
We also hear a little bit about gallium arsenide,
and there is a chance that gallium arsenide
will become a significant driving
force by the end of the decade.
But at the present moment, it's silicon and principally CMOS
technology.
These chips are presently made as relatively small bricks
about 1 centimeter by 1 centimeter on a side
and less than 1 millimeter thick.
But when you look inside a PC, as we're now doing,
you don't see chips per se.
What you see in the packaged result of the chips.
The chips are inside these objects
that are scattered about on this board here.
What we really need to do is, at the present moment,
look at what those technologies are.
Now this slide is an alphabet soup of the types of acronyms
that the packaging engineers are presently using today.
Most of the PCs, for example, are
made by putting dual in line package, that's DIP, on PCB's,
printed circuit boards.
And there are a number of ways of doing that, but typically
you mount the device and the actual chip, that we're talking
about, is that green rectangle within that protective box,
as it were.
And that green rectangle box can either be mounted
on the surface of the printed circuit board, as with surface
mount technology, SMT, or it can be
plugged through holes in the printed circuit board
as is with PTH, pin through hole technology.
Now, there are many other ways of packaging device other
than dual inline package.
There's a small outline package, or there's pin grid array, PGA,
or there's quad flat pack, QFP.
These are the kinds of packaging technologies
that are presently available.
But, what we need to do is look forward
to new packaging technologies that
are going to enable much denser connections coming
from these chips.
This is an example of TAB technology,
for tape automated bonding technology,
and this is the kind of technology
that we'll be talking about in this presentation.
So what is packaging and interconnect technology
after we've got this far?
Most systems consist of an assembly of integrated circuit
chips.
The chips need to communicate to one another
and to the outside world.
The chips need power to work.
They need to be cooled.
And those chips need to be protected.
And this is what packaging and interconnect technology is all
about.
So now let's look at the design forces, the driving forces,
that are involved in making the right choices for the packaging
and Interconnect technology, how you
put the chips into the system.
It's a good idea to look where the chip technology is headed,
and let's look forward to the year 2000.
We can expect chips that will be running with a 200 megahertz
cycle time.
That's compared to where we are today
of maybe 30 or 40 megahertz at the very best.
We're looking forward to larger devices.
Instead of the 1 centimeter, we'll
be up at 2 and maybe even 3 centimeters.
We're going to be looking at more I/O, that's
a number of pins, that's a number of connections,
that come off the chip.
At the present moment, maybe chips go up to 400 I/O.
We'll be looking to over 1,000 by the time
we get to the year 2000.
And also these chips are going to be hotter.
Presently chips may be no more than 5 watts.
Now, we're talking about looking forward
to having 50 watt chips.
So we're going to be, in summary, 10 times faster,
maybe 2 or 3 times larger, maybe 2 or 3 times more I/O,
and certainly almost 10 times hotter for these chips.
That's the challenge that we face.
Where the system's heading?
Well we've already said some things about this.
They're going to be faster.
They're going to be more powerful.
We've already seen a progression of 5 megahertz
to maybe 30 megahertz with regards to PCs.
And we've got to ask ourselves, now,
what's needed beyond that single chip packaging on the printed
circuit board, that we've been talking about.
Now, in the past the supercomputer manufacturers,
the mainframe manufacturers, have
found that as they went above 50 megahertz
for their system clock, they needed
to go out of the single chip packaging and PCB.
They needed to go to something called multi-chip module
technology.
And that's what I'm going to be talking
about for the rest of this talk.
Let's just look at the microprocessor chips
to put this all in perspective.
Here are some historical trends of microprocessor chips through
the decades of the 70's and 80's, going into the 90's.
There is no reason at the present moment
to not expect that this chip technology will continue
to improve in performance.
And so, you can clearly see that by the year 2000,
the performance expectations of microprocessors
are going to be well over 100 megahertz.
There are very good cases that it could possibly
be over 1 gigahertz, 1,000 megahertz.
Now the conventional single chip packaging, it turns out,
cannot handle the high I/O and it's not cost effective.
At the present moment, the best packaging technology
for handling high I/O is the pin grid array, the PGA,
and it does a reasonably adequate job,
but it is too expensive.
And as we go to wanting more and more I/O off the chip,
that pin grid array is going to get larger and larger and more
and more expensive.
We're finding, therefore, that this high speed single chip
packaging is too costly.
And, furthermore, the printed circuit board
that this chip technology, this single chip packaging
technology, has to connect to also
becomes too costly and too complex.
Let's look at how much area the chip packages take up
on the printed circuit board.
And, so, on this graph here on the left hand side,
we have the card area.
You could think of that is the area occupied by the packaged
chip on the board, and, as you see,
it runs from 0 to 25 square centimeters.
And, on the horizontal axis, we have a logarithmic scale
of the package pin count.
You can see from this graph that, really, the dual inline
package is lost, if you want to have more than 64 I/O
from a particular chip.
It just begins to consume too much area on the board,
and so you have to move to some of the packaging technologies
further to the right on this graph.
Pin grid array, there, is in the middle of that band, broadband,
there.
And, certainly, pin grid array can fairly effectively
package devices that have maybe 250 maybe even 500 I/O.
But if you really want to push off the right hand
side of this graph, as it looks that chip technologies are
going to, then you're going to have
to look in other directions for the connection and packaging
technology.
And that's where I think that TAB technology is going
to play an important role.
That's that T-A-B there for tape automated bonding.
And that board that I referred to,
the way that you get the interconnectivity in the board,
that is all the wires that need to connect
between these packaged chips, the present way of doing that
is to increase the number of layers in the board.
This is a historical trend showing through the late 70's
and through the 80's, how the number of layers in the board
has increased, that's the blue line.
And you can see that as we entered 1990,
we were getting close to 100 layers
within the printed circuit board.
The board also gets substantially thicker and much
more difficult to make, because one way of making the printed
circuit board requires that you drill holes through that board
to get the connections that run vertically
between those layers.
This particular technology becomes increasingly complex
as you can see and very expensive as a consequence.
We have to look for cheaper solutions.
Now, you may ask, why not go to wafer scale integration?
Why cut up these chips into small units?
Why not make one large big chip?
The simple answer to that is, at the present moment, the way
that we see that we can go, it's going to be too expensive.
You cannot yield large chips sufficiently well.
The other problem with wafer scale integration
is usually different technologies are required
for different functions.
You usually need a different integrated circuit technology
for logic, than you do for fast cash,
than you do for dense memory.
And it's very difficult to come up with an integrated circuit
process that satisfies all those requirements,
such that you can put all those kinds of functions
on one big chip.
That's why I don't think wafer scale integration
is going to be the solution.
Even if it was, it's still going to need a package
to protect that wafer from the environment,
to connect that wafer to the outside world,
to provide power, and to provide cooling.
Let's look at the electrical performance,
and see what direction that drives us,
and to see why that drives us in the direction
of the multi-chip module.
When you have a typical operation in the machine,
the data exits registers.
You go through a certain number of logic decisions
on a number of chips.
You may send an address over to the memory.
You may fetch the data from memory,
and then end up that cycle by loading that information
into a register.
That's a typical machine cycle.
That's the type of thing that has to be
done in one tick of the clock.
Now, if you look at present mainframe systems,
back in the early 80's, IBM introduced a 3033 machine,
and that was built in single chip packaging
on printed circuit board.
And that had a cycle time of 57 nanoseconds.
In order for them to be able to come out
with their next machine, which is
the 3081, with a substantially improved cycle time,
down to 26 nanoseconds, they really
had to shrink the package component of the delay.
And they did that by going to multi-chip module technology.
Now, why did they have to shrink?
Why did they have to go to multi-chip modules?
To get an answer to that we have to introduce
into this discussion the velocity of light,
the rate at which signals can propagate
throughout the system.
You're probably well aware that the velocity of light
is such that in one nanosecond light in free space
can travel about 30 centimeters or one foot.
Now, usually in electronic systems
that we're dealing with, the dielectric constant
is in the range of maybe 3 to 5 or maybe as high as 10.
And so, the actual speed of signal propagation
within computer systems is usually about a third
of the speed of light, which means
that you can go about 10 centimeters in 1 nanosecond.
So, if you really want to have systems that are running fast,
that have small delays between the components,
you have to make that computer system relatively small.
Otherwise, you'll just be losing out to the velocity of light.
Now, we need to look at the signal fidelity
as we send signals between the chips.
If the risetime of the signal, the rate at which the signal
rises from at 0 to 1 state, is substantially longer
than the path length, then you, essentially,
end up by just charging the output capacitance,
or the capacitance of the net.
I'll give an example here.
If the net is 5 picofarads and the output impedance
of the device is 1,000 ohms, then the RC time constant
is going to be about 5 nanoseconds.
And this is shown diagrammatically here.
On the left hand side, we have a driver shown a Thevenin
equivalent for that driver that steps up in voltage,
but the output, as indicated, rises
with the time constant of RC.
We have a typical exponential rise
of the signal at the receiver end, which is the right hand
side of this graphic.
Now, as we go to faster signal rise times,
we've got to look at transmission line effects.
Now, that's probably not necessary for CMOS.
CMOS typically, at the present moment,
still has a few nanoseconds for its risetime.
But, ECL is a sub nanosecond technology.
ECL is emitter coupled logic, and it
has rise times of the order of 100 or 200 picoseconds,
at the present moment.
Both of these technologies are going to get faster as we go
through the 90's.
And CMOS is very rapidly going to get
into the subnanosecond risetime regime.
And so, the issues of sending signals on transmission lines
is going to be important for both bipolar technologies
like ECL as well as CMOS technology.
So, let's think about transmission lines.
We're talking about sending signals
that have risetimes that are short compared to the length.
For example, a 200 picosecond risetime signal
going into a line 10 centimeters long, which would have
a delay of one nanoseconds.
Now we're sending energy into that line,
and that energy can echo around, and that causes some problems
that we're going to talk about.
Generally speaking, though, we're
usually OK to assume a TEM mode for the transmission lines,
at least at the present moment.
When we start thinking about going above 1 gigahertz,
maybe we even have to be more sophisticated than that.
So here's a transmission line.
We send a signal from the left hand side, here, and the signal
as it arrives at the right at the receiver sometime later,
just given by the delay of the transmission line.
But, generally speaking, with an ideal transmission line,
the risetime of the signal is preserved
as we send that signal through the transmission line.
So that's the ideal system.
That's what we would like to see in our computer systems
that we put together.
What happens in reality is we get a mess,
looking something like this.
The waveforms that get sent and received are very messy.
They have lots of bumps and dips, reflections, echoes.
This is a significant concern in designing a system,
because these bumps and dips on the waveforms
can cause erroneous switching of devices.
We have to understand where that comes from.
Now, when you really look at the transmission lines,
you're sending a signal on down, let's say, line 1.
But, you have another line in close proximity to that.
But those transmission lines are not independent of one another,
they are coupled to one another.
And I've shown very simply here the coupling,
in terms of a mutual inductance, L sub
M, and the mutual capacitance C sub M.
And these inductances and capacitances,
these mutual terms, need to be compared to the self inductance
and self capacitance of the transmission line L S and C S.
Now this coupling between two parallel lines,
which occurs very typically within
the interconnect technology between the chips,
leads to crosstalk.
And there are two forms of crosstalk.
One is forward wave crosstalk, where
you get a signal that propagates on the quiet line
and that signal is a blip, a discontinuity,
a jump in voltage, that propagates
along the quiet line in parallel with the driver line signal.
And the magnitude of that foward wave crosstalk,
is determined by a difference between
the inductive mutual coupling and
the capacitive mutual coupling.
So, if somehow you can engineer that those two
terms in parentheses, there, the first and second term
are equal, then you can actually cancel out the forward wave
crosstalk.
The other form of crosstalk is backward
wave crosstalk, which appears as a step on the quiet line that
stretches out behind the propagating edge on the driving
line.
Here, I show the equation for backward wave crosstalk.
And, now you see those two terms in the parentheses
are added together.
And, so when we have no way of canceling out
this backward wave crosstalk, the only way
that we can reduce the magnitude of the backward wave crosstalk
is to reduce Lm and Cm.
And the best way of doing that is
to move those lines further apart, which
runs counter to our requirement of trying to get as many lines
into a smaller space as possible.
What I show here is just one simple step
that is propagated along one line, that's
the purple outgoing waveform on the top graph,
and the received signal at the end of that line.
You see there is still a significant amount
of distortion here.
What I'm trying to do with this slide
is to show where these two crosstalks come in
and have an effect.
If you look below, we're looking at the signals
on the sending end and the receiving
end of the quiet line.
The received signal, the orange waveform with a blip,
is the forward wave crosstalk that appears at the far end.
The increasing signal at the near end,
which is that turquoise color, is the backward wave crosstalk
that's observed at the sending end on the quiet line.
These are the types of effects that
have to be taken into account in designing
the interconnect technology, that connects
the signals between the chips.
Now in addition to just the transmission
line effects that I've talked about,
we have to consider the discontinuities
in that transmission line.
And those discontinuities come through vertical veirs
within the interconnect technology, or, in particular,
the connections that are made between the chip
and the interconnect, or the connections
that are made between one portion of the interconnect
and the next as we go through a connector.
So we're talking about the discontinuities associated
with chip connections, connectors, and veirs
in the interconnect.
And these discontinuities usually
look like an inductive, L, or a capacitive, C, discontinuity
in an otherwise relatively uniform
characteristic impedance, Z 0.
Now it turns out that usually the inductive discontinuities
in the system by far outweigh the capacitive discontinuities
in the system, as I indicated at the bottom.
So let's just look at the effects of inductive coupling
between discontinuities and let's
consider, for the present moment,
two connections that go to a chip.
I've got one connection where I'm sending a signal.
I've got a parallel connection, where at the present moment,
we can assume it is a quiet connection.
Now on the driving line, I have a rate
of change of current d I by d t, there,
but on the sensing or the quiet line
I induce into that, essentially like a transformer,
a coupled signal, d V s, as I've indicated in this slide.
Now, we can relate d V S to the driving current rate of change
through the mutual inductance, and that's
what's shown at the bottom of this slide.
Now we can get an idea of the magnitude of these terms
by looking at some simple types of signals.
And just for simplicity, let's assume
that the driving signal is an exponentially rising step
function.
So, we've got V 0 e to the minus t upon Tor.
Now the drive current, because we're
dealing with a transmission line with a characteristic impedance
of Z 0, I d is the drive voltage, V d divided by Z 0.
The induced voltage in the adjacent line,
due to this inductive discontinuity,
is as shown in the next equation.
We've got the factor of 2 there in the denominator,
because that disturbance that is induced
into this inductive discontinuity propagates
away in both directions, towards the driver
and towards the receiver.
So that's where the factor of 2 comes from.
Substituting for d I by d t in that equation,
we now get the magnitude of the disturb on the quiet line,
is given by the mutual inductance divided by 2 Z
0 times t.
And this t in this particular case
is a time constant of the exponential.
So if we plug some figures in here,
which are fairly typical, if we think of a chip
connection, which could be a wire bond or a TAB connection,
the mutual inductance might be about 500 picohenrys.
We'll typically deal with systems
of the characteristic impedance of 50 ohms.
And let's say we have a risetime of the order of 500
picoseconds, and plugging it into that equation
we can expect a disturbance due to this inductive coupling
between these discontinuities.
We can expect a disturbance of 1%.
Now, that's 1% from the line to the left.
If there is at the same time a simultaneous signal
on the line to the right, there's another 1%
coming from that.
And, so that these discontinuities
can, in principle, add up the disturbances
on the quiet lines.
And this is one of the things that you
have to be very careful with and is a significant factor in how
you design the systems.
Now while we're talking about these inductive
discontinuities, let's just look at one other area
that causes a lot of headache, and that
is the power delivered.
Usually the voltage rails that go to a chip
are between 1 and 5 volts.
And you require a voltage regulation
to be better than 10%.
We want to avoid false operation from power disturbs.
Those power disturbs are generally
caused by the inductance of the connection of the power
to the chip.
A good example of this problem is in your home environment,
if you don't have a very good power distribution
system to your house.
Whenever the compressor on, shall we say, your refrigerator
turns on, it draws additional current from the power supply.
If you don't have a good connection to the power supply
there's too much inductance in that,
then, as that compressor turns on,
then maybe the picture on your television
shrinks because the overall power delivered
to all the other items that you have in your house
instantaneously drops.
This is the kind of brownout effect that you might have.
You can have that on the chip.
It is a very severe problem.
It is one of the most challenging problems
to the designer of the package system,
to the designer of computers, in fact.
Usually the significant event that causes power disturbs
is simultaneous switching, when a particular chip
has to send a whole world of information to another chip.
That means all the off chip drivers are switching together,
that's the simultaneity factor.
They all switch together.
They all are suddenly demanding additional power from the power
supply, and if there are substantial inductance
in that power supply connection, then the power
will instantaneously drop to the chip.
This is the Delta I problem, and it's once again
related to the inductance of that connection of the power
to the chip through the usual equation
for inductive discontinuities.
Here's a diagram to try and illustrate how that happens.
We have an active driver.
It tries to send a signal off the chip
into that transmission line.
As the active driver switches, because of the inductance
in that connection of the power supply to plus V there,
the power drops momentarily to the active drivers.
That has the effect of causing some distortion on descent
waveform from the active driver.
It also has an effect upon quiet circuits.
Circuits that are not actually switching
at this point in time.
You get disturbances propagated out from quiet drivers,
for example.
And, so the active receiver sees a distorted waveform.
The quiet receiver sees some distortion,
which is sent to it, because the quiet driver
was disturbed through the power supply connection.
This is a significant challenge as we go to high performance
systems to worry about these power disturbs
and to minimize these power disturbs.
For the remainder of this presentation,
I'd like to look at the future directions for packaging
technology in particular illustrate that with the work
that we're doing MCC.
And so let's start with a picture on the puzzle box.
What does a multi-chip module look like?
Here's an example of some work that we've recently completed.
It's a multi-chip module approximately 2 and 1/2 inches
square and contains 18 chips.
It is a dual avionics 1750 A signal processor.
That's nothing more to say than it's really like a PC,
but it's a PC that finds its way into many pieces
of military avionics.
What you see here are the bare chips attached
to a high density interconnect.
So instead of taking the chips, putting it in a single chip
package, and then connecting those chips on a printed
circuit board, what we do now is we try and cluster
as many chips as we possibly can within, in this particular
case, a 2 and 1/2 inch square box,
and connect those chips together, and only
have a relatively few number of I/O
or interconnections out to the next level of package, which
typically could be, once again, a printed circuit board,
but, nonetheless, could be a far simpler printed circuit board,
than if we'd taken these chips, put them
in single chip packages, and then connect those ships
directly to the printed circuit board.
So this is the kind of technology
that I'm going to be talking about for the remainder
of this talk.
What's our driving force for the technologies
that we're putting together?
We've adopted a superworkstation as a driving
force for this work.
We're looking at the future of desktop computing if you will.
What is the engineer going to be using in the mid 1990's,
or what is the engineer going to be using by the year 2000?
So let's consider what a superworkstation for the 90's
might look like.
One of the attributes is it's going to be very fast.
We have chosen a 3 nanosecond cycle time
as the goal for our activity.
3 nanosecond cycle time means that this system
will be running with approximately a 300 megahertz
clock.
How big should the system be?
One measure of bigness of the system
is, how many gates are going to be in the CPU.
We want to package 10 million gates within the CPU.
10 million gates is approximately 2,
3, maybe 4 times larger than present supercomputers.
Whether it's a uni- or a multi-processor I don't know.
Let's just for the time being consider a uni-processor
of 10 million gates running with a 3 nanosecond cycle time.
One of the things that we first need to consider
is how does the multi-chip module get us
over that 50 megahertz barrier.
Here's one view of what the packaging
technology of that superworkstation
would look like.
I show 4 multi-chip modules connected together in a stack.
Each multi-chip module would contain, let's say, 25 chips.
Therefore, each multi-chip module
would contain maybe 2 and 1/2 million gates.
Each module needs to be removable,
as I've shown with that third module there being removed.
There are connections that have to run between the modules,
and I show those connections going through this side
panels on either side.
We have to work out how we are going to power
and cool these modules.
And cooling is going to be a significant challenge.
I want to keep this overall geometry
of this cube of computing here to be
approximately 10 centimeters high, 20 centimeters wide,
and 10 centimeters deep.
In other words, it's a 1 liter volume
that is the heart of the CPU.
Why one liter?
Because we have to go back looking
at that velocity of light.
If I have 10 centimeters on this side
to communicate anywhere in this machine
to anywhere else, the maximum distance
that I'll have to run with Manhattan paths of avenues
and streets and up and down skyscrapers, if you will,
is going to be 30 centimeters.
And that's a maximum distance I can
go, considering the usual velocity of signal propagation
within computer systems being approximately C upon 3.
Let's look at what multi-chip modules are in existence,
at the present moment.
The first to introduce multi-chip modules
were the mainframe and supercomputer manufacturers,
and IBM is a very good example.
Back in the early 1980's, IBM introduced
their TCM, their thermal conduction module.
It was a multi-chip module based on building the interconnect
in a monolithic slab of alumina with molybdenum interconnect.
And it was really made up of lots of ceramic layers
laminated together.
The actual interconnect itself had a characteristic impedance
of approximately 55 ohms and yet on the other hand,
it was quite resistive because they were using molybdenum.
They connected the chips by putting solder balls
on the chips and flipping them, and reflowing that solder
to connect the chips to the surface
of the monolithic alumina substrate.
Cooling was done with pistons that
rested on the back of the chips to conduct the heat to a water
jacket.
One of the concerns is the TCE, the thermal coefficient
of expansion, of the different materials that are used
within the packaging structure.
On the one hand, we have silicon,
the silicon of the chips, which expands
at approximately 3 ppm per degrees C.
And, then on the other hand, you have the package with alumina
which is 7 ppm, and the moly within that,
the moly for the actual conductors, which is 5 ppm.
So as the system heats up and cools down,
various portions of the system shrink or enlarge
at different amounts.
And this is a significant challenge
to work with, to ensure that there
are no reliability problems with the shrinking
and expansion of various parts of the system as you
go through the operation and use of these systems.
The solution to multi-chip modules
that IBM adopted in the early 1980's is
shown diagrammatically here.
The chips are connected to the alumina substrate
through their solder ball technology, called C4.
The heat is removed from the chips by conduction
through the pistons through the hat to the cold plate.
And the cold plate is kept cool by actually
flowing chilled water through channels in that plate.
This is the approach that IBM took.
It turns out that it is a very expensive approach
to the building of the multi-chip modules.
It's not too expensive that you cannot use it
in a supercomputer or a large mainframe,
but it's certainly much more expensive than the kind
of technology that you'd want to put in that simple workstation
of the 1990's, or eventually into a PC of the year 2000.
So let's look at the requirements that we might have
on the cost of the packaging technology for that
superworkstation of the 1990's.
Typically in that time we'll expect
that chips are going to cost maybe $25 each.
So with 100 chips in that system,
$2,500 is going to go into the cost of the chips.
Now I estimate that the packaging technology
must account for no more than maybe $1,200 or $1,500
in addition to the cost of those chips.
So I've presently budgeted here $1,200 for the packaging
into those four multi-chip modules
that I had in the diagram of the stacked modules.
Maybe an additional $300 for the connectors and the printed
circuit board that these modules may be communicating with.
And then maybe another $1,000 need
to be budgeted for how we're going to test this system,
for the functional test of the components like the chips,
the subassemblies, like the multi-chip modules,
and for the complete system.
So the cost breakdown of our superworkstation
would look something like this.
1/2 of the cost is going to go in the chips.
A 1/4 of the cost is going to go in the package.
And the remainder is going to be in the testing.
So we have something like a $5,000 cost
for this superworkstation.
So what are the challenges to this system?
I put a lot of emphasis on cost, and I
think that's an important message
that I want to get across.
There is always, generally speaking in this area,
you can always find a technical solution to a problem.
It turns out that many technical solutions.
Our far too costly, and it is the low cost solutions
that are going to be the effective solutions, that
are finally going to find their way to the marketplace.
So it's very easy to get blinded by great technology.
You can lose sight of the market needs.
You've got to focus on cost and that is really the challenge
that we're trying to tackle at MCC at the present moment.
And let me give you some examples of the technology
and where those cost and performance
requirements come to play.
For the interconnect between the chips in the multi-chip module,
we've chosen an approach which uses copper and polyimide.
So that's the acronym at the top there, CuPI, copper polyimide.
And we've adopted an approach that we believe will ultimately
lead to a very low cost manufacturing
of the high density of interconnect,
that is needed to run the communications
between the chips.
We're taking an approach of plating for making up
the copper layers.
We're taking an approach of very simply polishing,
for planarizing the structures.
As you build up multilayered structures,
they can very easily and very rapidly
get out of being planar.
Because of the patterning of the structures that you're making,
you end up with non-planar structures,
if you're not careful.
And so, we've adopted the approach of polishing
for achieving the planarization.
We're typically making conductors
that are 5 microns thick and maybe 15 microns wide.
Similarly the insulator, the polyimide
in this particular case, is of the order of 15 microns thick.
With the kinds of structures that we're building,
then, we end up with transmission lines
used for communicating between the chips.
Transmission lines that have a characteristic impedance
in the range of 50 ohms.
It can be as low as 40, it can be as high as 70 or 80.
It depends on what you want to do as far
as how you want to design it.
We find that this kind of structure
is very suitable for passing signals with risetimes
of less than 200 picoseconds.
The bottom of the slide I've introduced
a new parameter, that of the thermal performance
of the package.
We want to try and achieve less than 1/2 a degree
C per watt per square centimeter for the cooling of the chips
for the thermal path between the chip
and where we've put the heat sink.
That means that a 10 watt chip 1 square
centimeter would be no more than 5 degrees
centigrade above the temperature of the heat sink.
Here's an example of the copper polyimide technology
that we're making at MCC.
First what you see, this is a section through it.
What you see at the very bottom is the rough surface
of the substrate on which this is made.
We're typically working with alumina.
We could use silicon.
We could actually use a metal.
What we build up are then, on top of that substrate,
are the layers that are going to be
used for the interconnect between the chips.
In this particular case, we've got 5 layers of interconnect.
We can call them x y, power and ground.
And then on top, we have the bond pad layer
where the chip connections are going to be connected to.
This is a kind of technology that we're building.
The line widths that you see there to the right
are of the order of 10 microns wide with a 10 micron spacing,
and they're about 5 microns thick.
These lines in this particular case
being only 10 microns apart are really too close.
And if you run those lines for too long a distance,
then you get into really significant difficulties
with regards to crosstalk, the backward wave
and the forward wave of crosstalk
that we've been talking about.
So, although in this particular diagram
I show 10 micron lines with 10 micron spaces,
we find that it is far more desirable to have something
like a 15 micron line and maybe a 30 micron
space between those lines.
The other important feature about this
is that you're able, with the plating technology,
to plate up the conductor, the copper, to connect
between these layers, these five metal layers.
You can plate that copper up vertically,
as is shown right down the middle of the slide, that
makes a very low thermal impedance
path between the chip, which is going to be attached
to the top of this slide and the base,
the substrate, which is the alumina
at the bottom of this slide.
There is a very efficient thermal path
from the chip to where the heat sink is going to be.
And it's necessary to use that copper in that fashion
to get that good thermal performance.
We are developing TAB technology for connecting the chips
to the high density interconnect.
TAB is, if you remember tape automated bonding.
And in this particular case, you take chips
and connect them to a 35 millimeter
format of copper conductors.
The chips are connected through a process
of inner lead bonding.
And that can be done with all the needs at once,
or it can be done on the lead by lead basis.
MCC has developed a method of laser bonding of these chips.
Here's an example of a chip connected to a TAB lead frame,
a tape automated bounded lead frame.
What you see here are the leads that connect to the chips.
They're actually a silvery color that
is a tin plated copper lead that is connected to the chip.
The next stage is to take and cut the leads and the chip away
from the tape frame, and then bond
them to the high density interconnect.
And this is a view of some chips or, the more precisely,
the corners of chips that have been connected to high density
interconnect.
You see the very fine connections that
are made between the chips.
The bars that are resting on top of those connections
are actually polyimide stiffening rings
to hold the leads in place before the connections
are made.
So from the top of the chip, the leads run out,
they are bent down, and then they
are connected to the top surface of the interconnect.
In this particular example, the leads
are spaced where they make connection to the high density
interconnect.
The leads of space at approximately 10 mils.
Now let's look at the cooling problems.
Now, one of the first things that we needed to decide
is we were thinking about this superworkstation of the 1990's,
is whether we would take an approach of liquid cooling,
or whether we could do it with air cooling.
Now, if you remember, I mentioned in the IBM TCM.
They had a way of conducting the heat to a water cool plate.
Now, you can certainly remove the large amounts of heat
that you can expect from the vintage 95 chips.
And you can improve the cooling efficiency of that cold plate
through such things as using microchannels.
What we have devised at MCC, though,
is a way of making microchannels for air,
efficient ways of dumping the heat from the chip
into the air.
What we've developed is a air cooling technology
called Zephyr technology.
But let's look at the liquid cooling technology
upon which it's based.
In this particular case, we show a very high enlargement
of channels that are cut into silicon.
Each of these channels are maybe 40, 50, or 60 microns wide
and maybe 200 or 300 microns deep.
If you flow water through these narrow channels
you can remove substantial amounts of heat
from the silicon.
This work was done in the early 1980's by Tuckerman and Pease
at Stanford.
This is a very efficient way of removing heat from the silicon.
The water stays in the laminar flow
as it flows through these channels.
There's no turbulence or insignificant turbulence.
It's a very efficient way of removing heat.
What we've done is we've taken these kinds of concepts,
and we've applied it to our cooling technology.
In this particular case, it shows a number
of heat sinks, which are air cooling heat sinks,
where we use some of the same principles.
We passed the air through these heat sinks.
We keep the air as much as we possibly
can in laminar flow, that is most
efficient from the point of view of transferring
the heat between the heat sink in the air,
and is also very important at being
able to keep down the noise of the cooling of the air.
One of the big problems with air cooling
is, as you push the air faster and faster,
you get into problems with vortices
and with non-laminar flow, and it becomes very noisy.
It requires a higher pressure head to push that air through.
It becomes a very inefficient system.
What we've been able to do here with these heat
sinks is to keep that air in laminar flow
and working very efficiently for us.
Here's a further example.
You see the very fine channels that the air
has to flow through.
The air actually enters in the center
and flows out down the two diagonal sides lower
in the picture.
We have been able to show that with this technology
that the supercomputer that we're talking about,
the superworkstation, can actually be air cooled.
We've shown that we can achieve less than 1.5 Kelvins per watt
per square centimeter of cooling performance
with this kind of technology, with very low acoustic noise,
less than 50 dBA.
That means that it is adequate.
It is suitable for putting in an office environment.
So we think the air cooling can remove the amounts of heat that
we will have in our supercomputer of the mid
1990's.
And one of the challenges now is to get
that connection, thermal connection,
between the chip and the heat sink.
Now I've already talked about the fact
that with our copper polyimide technology
we can put thermal veirs vertical copper conducting
paths from the chip through the interconnect.
And these thermal paths together with the high performance
of the air cooling will satisfy our requirements
with this superworkstation of the 1995 time frame.
With the new technologies associated
with multi-chip modules, it is important to also look
for a breakthrough in the time to market.
Time to market becomes extremely important.
Design iterations at the present moment
can take far too long, over a year.
We need a way of fast prototyping hardware.
We need a way of rapidly getting new designs into manufacturing,
because rapid demonstration of capability
wins contracts and customers.
We have developed at MCC one way of doing this
with something that we call quick turnaround
interconnect, QTAI.
Rather than defining each level in the structure
of the interconnect, we predefined power, ground, x
and y signals.
Such that they are the same for all applications.
And what we do is we just personalize
for a specific application by putting links on the surface
and defining where the paths are,
as is shown in the next slide.
So what we have with the dielectric layers
and the buried wire segments is an unpersonalized array
of interconnect, which we can now
personalize with surface links.
We can do that personalization in only a matter of a few days.
So with the personalization of a few days,
you can then assemble the chips onto this interconnect
and be testing a new prototype within a week.
So this gives us a way of very rapidly prototyping
new designs.
This particular design was built in that fashion.
We have built an early version of our array of interconnect,
our QTAI.
We have then routed and designed where
the links need to go to connect all the x segments and the y
segments to connect between these chips.
In this particular case, we have connected 16 VLSI chips
onto the top surface of QTAI interconnect.
This particular multi-chip module
is once again approximately 2 and 1/4 inches square.
This is the kind of approach that we believe is necessary
to get quick prototyping as well as rapid entry into production
of new technologies, of advanced technologies,
technologies that are going to be appropriate
for the superworkstation of the 1990's.
So with this, I would like to conclude.
In the 80's, we have seen rapid advances in chip technology
and maybe less in packaging technology.
As we move into the 90's, there are
going to continue to be rapid advances in the chip technology
and the package technology has to catch up.
We believe that the main approach in the packaging arena
is going to be with multi-chip modules.
I do believe that multi-chip modules will
be used in workstations and PCs by the end of this decade.
So what we've got to do is we've got
to work out how to dramatically reduce
the cost of multi-chip modules.
It all seems to be possible with today's knowledge of materials
and manufacturing.
All that remains to be done is to do it.
Thank you.
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