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[MUSIC PLAYING]

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Hello.

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I'm [INAUDIBLE],, IBM Resources
division's vice president

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of systems and software.

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I would like to talk to you
about the Power Visualization

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System and its associated
software, Data Explorer.

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What I really would
like to discuss with you

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is what we had in mind--

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invention, discovering,
human problem-solving.

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These are unique human
capabilities, highly prized,

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yet fairly not well understood.

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Over the next decade, the
amount of computing power

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that we will get from better
microprocessors, larger

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memories, will increase the
amount of computing power

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that we can dedicate to both
simulation and visualization,

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and really change qualitatively
the way we solve problems

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with computers, in a sense,
amplify our own capabilities;

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amplify, if you would like
to think about it this way,

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our intelligence.

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The cycle of problem-solving
involves iteration.

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We try out an idea
and like to see

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it result in a way that
is intuitively appealing

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and then try something else.

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The time it takes to
go through this cycle

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is of great importance
to determine

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whether this is a
useful paradigm,

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and indeed, will accelerate
our problem-solving.

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Man has an uncanny ability to
detect the most minute path

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in an image, and
see, gain insight,

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where a computer
could not find it

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after billions of calculations.

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So this paradigm really
takes what we can do best--

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detect patterns,
see connections,

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and connect it with the ability
of the computer to crunch

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through numbers at increasingly
faster and faster speeds.

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Armando Garcia will
be describing to you

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the system in great detail.

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I would like to simply say that
the initial set of applications

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that we have found
indeed demonstrate that I

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think we're on the right track.

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And it's very hard to tell
what the human mind can

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do and amplify it with
such computational power

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and capabilities.

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But I am confident it will be
nothing short of spectacular.

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Hello, I'm Armando Garcia.

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I'd like to tell you about the
IBM Power Visualization System

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and Data Explorer, two
innovative products that

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were conceived at IBM Research
and brought to the marketplace

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in under two years.

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Let me first give you
an outline of my talk.

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First, I will cover general
visualizations concepts,

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as well as our unique
approach to this problem.

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Second, I will describe
the hardware components

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of the power
visualization system

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and our rationale for
their unique design.

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Third, we'll see some actual
application examples that

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have been computed on the PVS.

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And finally, I'll summarize
where visualization is today,

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and where we at IBM envision
it will be in the future.

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So what do we mean
by visualization?

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Well, think of visualization
as a means of analysis.

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It allows us to study data from
complex computer simulations

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or from observational
experiments

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in a simple visual way.

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For example, a chemist
can interactively

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study the molecular
structures of a drug

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and how it may interact
with other molecules.

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Petroleum geophysicists
can graphically

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see the result of oil and
natural gas exploration

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experiments.

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For these experiments
cubes of raw data

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are gathered from
seismic observations

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and then analyzed using
visualization techniques

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to precisely locate oil
and natural gas deposits.

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By analyzing atmospheric
observations gathered

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from satellites,
climatologists can visually

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study the depletion of
the Earth's ozone layer

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over many years.

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Visualization is also a
means of extracting knowledge

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from complex data.

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It gives us the ability to ask
"what if" kinds of questions,

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to understand data
in a visual way.

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It makes use of the human visual
system, its enormous capability

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to absorb and comprehend complex
data in a pictorial form.

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For example, this visualization
of the airflow over an F-15

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wing clearly illustrates
where the pressure of the wing

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is greatest.

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Rendering this
data is important,

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but realization is where
the important discoveries

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can be found.

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Through the use of isosurfaces,
streamlines, and streak lines,

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this airplane wing
can be designed

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and tested over and
over without the cost

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of building a physical model.

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Visualization is also a
way of synthesizing data.

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Take, for example, this
photorealistic rendering

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of an automobile in a virtual
showroom as shown here

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on the monitor.

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This image sequence
was rendered on PVS

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using the alias parallel
ray tracer frame by frame,

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and is being played back
in real time from disk.

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Furthermore, visualization
is being used extensively

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in special effects for
television commercials,

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theatrical films,
and even theme parks.

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I'm sure you have seen movies
like Terminator 2 or Batman

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Returns and so forth, which have
used extensive special effects

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or visualizations.

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The PVS was conceived
to offer a new solution

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to the interactive
visualization process

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and to leapfrog beyond the
capabilities of today's

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approaches.

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Typical systems used
for visualization

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include workstations
and supercomputers,

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each having certain
advantages and disadvantages.

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Workstations are
inexpensive, and therefore,

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accessible to many people.

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They provide interactivity,
but obviously lack

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processing power.

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They can only handle
small data sets

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because of their limited memory,
the storage and bandwidth.

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And they are limited to simple
visualization techniques, given

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their hardware-based
rendering capabilities.

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Supercomputers,
on the other hand,

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are very expensive,
and therefore

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available to few people.

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They are usually not
interactive, what we refer to

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as batch visualization.

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However, they can
support large problems

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because they have the processing
power and I/O capability

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needed, and they can utilize
complex visualization

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techniques.

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However, they usually tend
to be application-specific.

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The Power Visualization
System represents

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an innovative approach to
interactive visualization.

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We wanted PVS to feel
like a workstation

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by providing the
interactivity and

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the user-friendly environment.

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We also wanted PVS to
feel like a supercomputer,

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to be able to handle
the very large problems

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and to be a cost-effective,
integrated solution.

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We also wanted to provide a
general purpose visualization

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tool that would be easy to
use, flexible, and extensible,

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so users across a wide
variety of application areas

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would be able to use the system.

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To build this
innovative system, we

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assembled an entrepreneurial
group at IBM Research.

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The group was made up of
researchers, developers,

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marketing, and business
operations people.

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We were only one location
isolated from the rest of IBM.

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So in effect, we were
like a small company

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trying to bring our
product to the marketplace

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in a short period of time.

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The result was the IBM
Power Visualization

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System and Data Explorer.

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My talk will concentrate on
the Power Visualization System.

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A separate tape is
available from IBM

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which describes Data Explorer.

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Let me now show you a few
visualization examples

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generated on our system.

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Seen here is a
visualization of the ozone

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density over the Earth depicted
as a pseudo-colored map image.

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This data was collected
by a NASA satellite

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and is shown in conjunction
with a coastline

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map of the continents with
some political boundaries.

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Low ozone density values
are represented in blue,

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while medium density values
are represented in green.

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We now show you a
morphing example

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in which we take this
raw static data set,

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apply a Cartesian to
spherical transformation,

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and use several redundant
techniques, including

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color, opacity, and height to
visualize the ozone density.

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Low ozone concentrations
are now depicted

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as blue, transparent
regions close to the Earth.

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We have also included a
detailed topographical map

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of the Earth, which
better illustrates

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the registration of
the ozone density data

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with our world map.

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This more advanced technique
can aid a scientist

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in identifying geographic
regions of interest

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during specific periods of
time for detailed analysis.

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This visualization
was performed using

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Data Explorer on the
Power Visualization System

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and stored as an animation
sequence on the disk array.

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You are seeing the animation
sequence being played back

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from disk in real time.

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Let's now look at
a more complex,

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time-dependent visualization
of the daily evolution

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of the ozone density over the
Earth through a 13-year period.

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The raw data set for
this visualization

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is over 900 megabytes in size.

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Later in the talk, you will
see additional visualization

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examples run interactively
on the Power Visualization

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System using the same data set.

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Let's now take a look at the
Power Visualization System.

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First, I'll briefly
introduce you

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to the three main
components, followed

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by a technical discussion on
the architecture and design

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of the visualization server.

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The system is comprised
of three main components.

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At the heart of the system
is the visualization server,

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which provides the
computational and visualization

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functions of the system.

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It is a parallel processor
with up to 32 general purpose

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CPUs, up to 2 and 1/2
gigabytes of memory,

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and high speed I/O
channels to communicate

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with high-speed devices.

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It uses ANSI standard
high-performance parallel

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interface channels, also
known as HIPPI channels,

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to communicate with
these various devices.

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Let me now tell you
about the disk array.

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The server attaches
to a disk subsystem

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which provides high-speed
data storage for the raw input

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data and the resulting
visualization images.

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This particular device uses 16
standard 5 and 1/4 inch hard

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disk drives, providing a
sustained data transfer rate

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of 55% megabytes per second.

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It is expandable from 21
gigabytes to 180 gigabytes

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by simply adding boxes.

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It also has a parity drive for
error recovery and a hot spare

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in the event that
you lose a drive.

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The last major
hardware component

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is the video controller.

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It attaches to an
R/6000 workstation

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and supports dynamic display
of the resulting images

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from the visualization server.

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It uses two distinct frame
buffers, an 8-bit buffer

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to support X-Windows and
Motif, and a double buffer,

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24-bit per pixel image
buffer, to support

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dynamic display of the images.

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Through the HIPPI channel, we
can transfer 25 million RGB

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pixels per second from the
server to the video controller.

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With this capability,
we can display images

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at a resolution of 1280 by 1024
at 20 frames a second, or HDTV

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resolution images,
which are 1920 by 1024

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at 12 frames per second, the
limitation being the HIPPI

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channel running at 100
megabytes a second.

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We also implemented a block
truncation code compression

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scheme, which is implemented in
software on the visualization

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server, and in hardware the
decompression being done

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in hardware in the
video controller,

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thus boosting the transfer
rate from 25 million to 200

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million RGB pixels a second.

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With this capability, we can
display full color HDTV movie

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sequences in real time.

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In addition, the
video controller

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can also support very
high-quality stereoscopic

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display using conventional
monitors or projectors

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at a rate of 120 hertz.

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Think of PVS as an
integrated system,

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which offers computational
and visualization services

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00:13:01,830 --> 00:13:03,960
to a network of clients.

256
00:13:03,960 --> 00:13:06,630
The visualization server imports
data from the high-speed disk

257
00:13:06,630 --> 00:13:10,020
array, performs a
visualization on these data,

258
00:13:10,020 --> 00:13:12,060
and then displays
the resulting images

259
00:13:12,060 --> 00:13:14,160
at the user workstation
on their X-Windows

260
00:13:14,160 --> 00:13:17,580
and Motif using a
client server model.

261
00:13:17,580 --> 00:13:19,680
I should point out the
data can be imported

262
00:13:19,680 --> 00:13:22,950
either from the high-speed disk
array, from the R/6000 support

263
00:13:22,950 --> 00:13:26,640
processor, or from anywhere on
the network using standard NFS

264
00:13:26,640 --> 00:13:27,960
facilities.

265
00:13:27,960 --> 00:13:30,810
Similarly, the resulting
visualization images

266
00:13:30,810 --> 00:13:34,380
generated on the server can be
transferred via HIPPI channel

267
00:13:34,380 --> 00:13:37,410
to an R/6000 attached video
controller, or through

268
00:13:37,410 --> 00:13:40,410
a standard Unix socket to any
workstation on the network,

269
00:13:40,410 --> 00:13:43,190
albeit a lot slower.

270
00:13:43,190 --> 00:13:45,880
The video controller also
supports a HIPPI daisy chain

271
00:13:45,880 --> 00:13:49,690
network, which handles up 32
workstations per HIPPI channel,

272
00:13:49,690 --> 00:13:52,990
and the server can address a
single workstation or multicast

273
00:13:52,990 --> 00:13:55,410
to a collection of workstations.

274
00:13:55,410 --> 00:13:57,850
In architecting the
visualization server,

275
00:13:57,850 --> 00:13:59,730
we had a number of
important characteristics

276
00:13:59,730 --> 00:14:02,760
which we felt were critical
to a well-balanced integrated

277
00:14:02,760 --> 00:14:04,330
system.

278
00:14:04,330 --> 00:14:06,880
By balance, I mean
the integration

279
00:14:06,880 --> 00:14:10,780
of high-performance processing
capabilities, memory capacity,

280
00:14:10,780 --> 00:14:15,560
and I/O bandwidth, as well
as internal bandwidth.

281
00:14:15,560 --> 00:14:17,960
Next was the idea of
making the visualization

282
00:14:17,960 --> 00:14:20,330
process completely
programmable without using

283
00:14:20,330 --> 00:14:23,850
any special purpose
hardware for rendering.

284
00:14:23,850 --> 00:14:25,890
The reason for this is simple.

285
00:14:25,890 --> 00:14:29,070
Visualization is much more
than simply rendering images.

286
00:14:29,070 --> 00:14:31,950
The realization component
can be quite complex

287
00:14:31,950 --> 00:14:33,690
and requires a
diverse collection

288
00:14:33,690 --> 00:14:37,470
of techniques which are not
easily mapped to hardware.

289
00:14:37,470 --> 00:14:40,740
Another reason was to support
advanced rendering techniques,

290
00:14:40,740 --> 00:14:44,070
such as transparency,
direct volume rendering,

291
00:14:44,070 --> 00:14:45,750
or ray tracing.

292
00:14:45,750 --> 00:14:48,210
This last capability
truly differentiates

293
00:14:48,210 --> 00:14:50,910
the Power Visualization
System and Data Explorer

294
00:14:50,910 --> 00:14:52,860
from other
traditional approaches

295
00:14:52,860 --> 00:14:55,260
by allowing us to combine
different rendering

296
00:14:55,260 --> 00:14:56,910
techniques in the same image.

297
00:14:56,910 --> 00:14:59,340
As for the choice of
the processing element,

298
00:14:59,340 --> 00:15:01,530
we decided to use an
off-the-shelf risk

299
00:15:01,530 --> 00:15:05,310
microprocessor rather than
implementing our own CPU.

300
00:15:05,310 --> 00:15:08,190
We chose an Intel i860 because
of its excellent integer

301
00:15:08,190 --> 00:15:11,100
and floating point performance,
and high-level language

302
00:15:11,100 --> 00:15:14,460
support using standard
C and Fortran compilers.

303
00:15:14,460 --> 00:15:17,400
In addition, it meant that we
could ride the technology curve

304
00:15:17,400 --> 00:15:19,590
and evolve the product
to use the next best

305
00:15:19,590 --> 00:15:21,720
available
microprocessor, including

306
00:15:21,720 --> 00:15:25,240
our own PowerPC microprocessor.

307
00:15:25,240 --> 00:15:29,200
Another architectural decision
was to use parallelism.

308
00:15:29,200 --> 00:15:32,320
One simple reason for this
was that visualization is well

309
00:15:32,320 --> 00:15:34,750
suited for parallelization,
and would therefore

310
00:15:34,750 --> 00:15:38,860
yield more effective processing
speed versus using a vector

311
00:15:38,860 --> 00:15:41,350
processing approach.

312
00:15:41,350 --> 00:15:44,410
It was also felt that
moderate parallelism would

313
00:15:44,410 --> 00:15:48,610
be manageable in terms of the
software and the system design.

314
00:15:48,610 --> 00:15:52,120
We chose to implement a simple
shared memory model, which

315
00:15:52,120 --> 00:15:53,950
offers an effective
way of supporting

316
00:15:53,950 --> 00:15:55,780
low latency and
fast communication

317
00:15:55,780 --> 00:15:57,370
between processors.

318
00:15:57,370 --> 00:15:59,620
It also offers a
cost-effective solution

319
00:15:59,620 --> 00:16:02,650
by providing large
global memory, therefore,

320
00:16:02,650 --> 00:16:04,690
handling large
visualization problems

321
00:16:04,690 --> 00:16:09,430
and coupling high-speed I/O
from the disk to the display.

322
00:16:09,430 --> 00:16:12,490
Finally, we chose to implement
a hierarchical memory

323
00:16:12,490 --> 00:16:15,970
architecture as an
effective way of providing

324
00:16:15,970 --> 00:16:18,520
low-latency and high
bandwidth communication

325
00:16:18,520 --> 00:16:22,300
amongst a moderate
number of processors.

326
00:16:22,300 --> 00:16:24,660
Each processor contains
a small on-chip cache

327
00:16:24,660 --> 00:16:26,400
for instructions and data.

328
00:16:26,400 --> 00:16:28,710
Local memory private
[INAUDIBLE] processor

329
00:16:28,710 --> 00:16:32,790
is used to hold code and
private data, such as the stack

330
00:16:32,790 --> 00:16:34,530
and non-shared data.

331
00:16:34,530 --> 00:16:37,560
This offloads the global
buzz from such traffic.

332
00:16:37,560 --> 00:16:40,500
Global memory is accessible
to all processors.

333
00:16:40,500 --> 00:16:42,480
An alternative would
have been to use

334
00:16:42,480 --> 00:16:45,150
a large second-level cache,
but we decided against it

335
00:16:45,150 --> 00:16:46,210
for two reasons.

336
00:16:46,210 --> 00:16:49,710
First, there was no mechanism
for maintaining consistency

337
00:16:49,710 --> 00:16:52,440
between the on-chip cache
and a second-level cache,

338
00:16:52,440 --> 00:16:54,600
given the chosen microprocessor.

339
00:16:54,600 --> 00:16:56,880
And second,
maintaining consistency

340
00:16:56,880 --> 00:17:00,070
across multiple caches,
say, 32, was not

341
00:17:00,070 --> 00:17:02,900
thought to be an
effective solution.

342
00:17:02,900 --> 00:17:06,140
Finally, the use of local
memory within each processor

343
00:17:06,140 --> 00:17:08,510
and shared memory
between the processors

344
00:17:08,510 --> 00:17:10,190
meant that we could
very effectively

345
00:17:10,190 --> 00:17:12,560
support other programming
paradigms, such as message

346
00:17:12,560 --> 00:17:13,550
passing.

347
00:17:13,550 --> 00:17:16,940
One of our design challenges
was to design a global bus that

348
00:17:16,940 --> 00:17:19,310
would provide low-latency
and high bandwidth

349
00:17:19,310 --> 00:17:21,800
communication between
a number of processors

350
00:17:21,800 --> 00:17:23,720
in a global memory subsystem.

351
00:17:23,720 --> 00:17:27,890
We also wanted the system to run
on a single 40-megahertz clock

352
00:17:27,890 --> 00:17:29,660
or above.

353
00:17:29,660 --> 00:17:32,300
The technical difficulty was
that traditional shared bus

354
00:17:32,300 --> 00:17:35,780
systems limit the number of
bus loads to less than 20,

355
00:17:35,780 --> 00:17:38,090
as limited by the
low current effects

356
00:17:38,090 --> 00:17:40,690
and the capacitive effects.

357
00:17:40,690 --> 00:17:44,830
In our case, we wanted to
support up to 32 processors,

358
00:17:44,830 --> 00:17:48,370
all accessing a common
global memory, in addition to

359
00:17:48,370 --> 00:17:52,870
high-speed I/O channels all
operating at 40 megahertz.

360
00:17:52,870 --> 00:17:56,320
Our solution was to use a
two-level shared bus structure

361
00:17:56,320 --> 00:18:00,010
with four nodes on each card
sharing a global bus interface,

362
00:18:00,010 --> 00:18:01,960
and to implement a
common global bus

363
00:18:01,960 --> 00:18:05,630
interface to couple the four
nodes to the global bus.

364
00:18:05,630 --> 00:18:07,250
Let me now show you
the architecture

365
00:18:07,250 --> 00:18:08,960
of the visualization server.

366
00:18:08,960 --> 00:18:12,680
It is a scalable system
containing up to 32 processors,

367
00:18:12,680 --> 00:18:16,160
a multi-bank global memory
subsystem providing up

368
00:18:16,160 --> 00:18:20,300
to 2 gigabytes of storage,
an I/O subsystem providing up

369
00:18:20,300 --> 00:18:22,670
to six full duplex
HIPPI channels,

370
00:18:22,670 --> 00:18:26,880
each capable of sustaining up to
100 megabits per second of I/O.

371
00:18:26,880 --> 00:18:29,030
And finally, a
host interface card

372
00:18:29,030 --> 00:18:31,820
that connects the server
to a RISC System/6000

373
00:18:31,820 --> 00:18:35,600
workstation, which serves
as its support processor.

374
00:18:35,600 --> 00:18:38,840
Connecting all the
components is a 1.28 gigabyte

375
00:18:38,840 --> 00:18:42,960
per second global bus
operating at 40 megahertz.

376
00:18:42,960 --> 00:18:45,690
Shown here is the back plane
of the visualization server

377
00:18:45,690 --> 00:18:47,850
which implements the global bus.

378
00:18:47,850 --> 00:18:51,390
Operating at 40 megahertz, it
can sustain a data transfer

379
00:18:51,390 --> 00:18:54,300
rate of 1.28
gigabytes per second

380
00:18:54,300 --> 00:18:58,610
using a 256-bit wide data bus.

381
00:18:58,610 --> 00:19:01,640
It supports up to
14 cards, and it's

382
00:19:01,640 --> 00:19:04,130
implemented as a controlled
and impedance transmission

383
00:19:04,130 --> 00:19:07,670
line with termination
at both ends of the bus.

384
00:19:07,670 --> 00:19:09,650
The bus interface
logic is implemented

385
00:19:09,650 --> 00:19:13,430
using 100K ECL technology,
which has the necessary speed

386
00:19:13,430 --> 00:19:15,790
and drive characteristics.

387
00:19:15,790 --> 00:19:19,210
The global bus uses a
synchronous decoupled protocol

388
00:19:19,210 --> 00:19:22,180
to support multiple
outstanding processor requests.

389
00:19:22,180 --> 00:19:25,360
Read requests are tagged with
a processor identifier, which

390
00:19:25,360 --> 00:19:28,090
is returned along with
the memory reply cycle

391
00:19:28,090 --> 00:19:30,390
to resolve its destination.

392
00:19:30,390 --> 00:19:32,490
Global bus arbitration
is implemented

393
00:19:32,490 --> 00:19:36,000
using a centralized, two-level,
round-robin arbitration scheme.

394
00:19:36,000 --> 00:19:39,630
Separate arbitration is provided
for the address and data buses

395
00:19:39,630 --> 00:19:42,510
in order to optimize the
use of the global bus.

396
00:19:42,510 --> 00:19:46,740
Thus, for example, a processor
read request and a memory reply

397
00:19:46,740 --> 00:19:49,500
can share the same
global bus cycle, given

398
00:19:49,500 --> 00:19:52,080
that the processor simply
needs the address bus,

399
00:19:52,080 --> 00:19:55,140
while the memory only
needs the data bus.

400
00:19:55,140 --> 00:19:57,900
Shown here is the
global bus arbiter card

401
00:19:57,900 --> 00:20:00,510
which also provides clock
distribution to all the logic

402
00:20:00,510 --> 00:20:02,070
cards in the system.

403
00:20:02,070 --> 00:20:04,260
To support interfacing
to the available bus,

404
00:20:04,260 --> 00:20:07,290
we architected a generic
global bus interface,

405
00:20:07,290 --> 00:20:09,810
which is used in all
the cards in the system.

406
00:20:09,810 --> 00:20:12,480
This interface deals with
a global bus protocol

407
00:20:12,480 --> 00:20:15,360
and provides a buffered
interface between the shared

408
00:20:15,360 --> 00:20:18,690
on-card bus with four local
nodes and the high speed

409
00:20:18,690 --> 00:20:19,770
global bus.

410
00:20:19,770 --> 00:20:21,510
For each of the
four local nodes,

411
00:20:21,510 --> 00:20:25,890
it provides an 8 entry FIFO to
buffer read and write requests,

412
00:20:25,890 --> 00:20:29,850
and another 8 entry FIFO
to buffer memory replies.

413
00:20:29,850 --> 00:20:32,160
This buffering helps us
support high bandwidth

414
00:20:32,160 --> 00:20:35,100
throughout the system and
to optimize the utilization

415
00:20:35,100 --> 00:20:37,360
of the global bus.

416
00:20:37,360 --> 00:20:39,640
Having shown you the back
plane, let me now show you

417
00:20:39,640 --> 00:20:42,940
the three main logic cards
and the visualization server.

418
00:20:42,940 --> 00:20:46,090
On screen right is the
4-node processor card.

419
00:20:46,090 --> 00:20:49,540
On screen left is the I/O
processor card with four HIPPI

420
00:20:49,540 --> 00:20:53,110
channels, and in the middle
is the global memory card.

421
00:20:53,110 --> 00:20:56,320
One card not shown is
the host interface card.

422
00:20:56,320 --> 00:20:59,050
Let me first point out the
common global bus interface

423
00:20:59,050 --> 00:21:01,660
section, which is essentially
identical in all four card

424
00:21:01,660 --> 00:21:02,930
types.

425
00:21:02,930 --> 00:21:04,510
There are three main sections--

426
00:21:04,510 --> 00:21:09,550
an address and control ASIC,
8 32-bit data path ASICs,

427
00:21:09,550 --> 00:21:12,340
and registered transceivers
providing level translation

428
00:21:12,340 --> 00:21:16,330
from the TTL on-card bus
to the ECL global bus.

429
00:21:16,330 --> 00:21:19,210
As you can see, these
cards are quite big.

430
00:21:19,210 --> 00:21:23,950
They're 20 inches by 23
inches by 113 mils thick.

431
00:21:23,950 --> 00:21:27,520
They have 10 signal layers
and six power plane layers,

432
00:21:27,520 --> 00:21:30,280
and they hold roughly
2,500 components--

433
00:21:30,280 --> 00:21:34,390
500 active components and
2,000 passive components

434
00:21:34,390 --> 00:21:38,440
comprised of capacitors and
bus termination resistors.

435
00:21:38,440 --> 00:21:41,360
We use a variety of through-hole
components and surface

436
00:21:41,360 --> 00:21:44,740
components, and there
are over 35,000 holes

437
00:21:44,740 --> 00:21:46,940
on each one of these cards.

438
00:21:46,940 --> 00:21:49,580
Now let's take a look at the
processor card architecture.

439
00:21:49,580 --> 00:21:52,940
It contains four identical
nodes and a shared global bus

440
00:21:52,940 --> 00:21:54,290
interface.

441
00:21:54,290 --> 00:21:56,390
Each node contains a
risk microprocessor

442
00:21:56,390 --> 00:21:58,520
with 16 megabytes
of local memory

443
00:21:58,520 --> 00:22:01,040
and a buffered interface
to global memory.

444
00:22:01,040 --> 00:22:03,980
This interface contains
a 32-byte read buffer,

445
00:22:03,980 --> 00:22:06,320
which reduces global
memory read latency,

446
00:22:06,320 --> 00:22:09,770
and performs bus width matching
between the 64-bit processor

447
00:22:09,770 --> 00:22:13,250
bus and the 256-bit global bus.

448
00:22:13,250 --> 00:22:16,850
Global bus snooping is used to
maintain buffer consistency.

449
00:22:16,850 --> 00:22:20,690
Similarly, a 32-byte write
buffer reduces global bus

450
00:22:20,690 --> 00:22:24,350
traffic by caching up
to 32 contiguous bytes,

451
00:22:24,350 --> 00:22:27,440
each validated by its
corresponding byte enable.

452
00:22:27,440 --> 00:22:29,840
These byte enables
are used to validate

453
00:22:29,840 --> 00:22:33,380
the update in global memory when
the right buffer is flushed.

454
00:22:33,380 --> 00:22:35,330
The block labeled
PBIF in the diagram

455
00:22:35,330 --> 00:22:38,240
is a custom ASIC which
supports a global memory

456
00:22:38,240 --> 00:22:41,290
interface and the local memory.

457
00:22:41,290 --> 00:22:43,930
To support a coherent
shared memory architecture,

458
00:22:43,930 --> 00:22:47,200
the on-chip processor cash is
enabled for local memory pages

459
00:22:47,200 --> 00:22:49,750
and disabled for
global memory pages.

460
00:22:49,750 --> 00:22:53,980
Thus, the average read latency
for a 64-bit load instruction

461
00:22:53,980 --> 00:22:56,230
is one cycle from
the on-chip cache,

462
00:22:56,230 --> 00:22:58,390
three cycles from
the local memory,

463
00:22:58,390 --> 00:23:01,390
and eight cycles from
the global memory.

464
00:23:01,390 --> 00:23:03,880
The global memory
subsystem consists

465
00:23:03,880 --> 00:23:07,300
of four cards, each with four
independent global memory

466
00:23:07,300 --> 00:23:08,930
banks.

467
00:23:08,930 --> 00:23:11,380
The memory banks are interleaved
across the global memory

468
00:23:11,380 --> 00:23:13,850
[INAUDIBLE] space using a
selectable memory stride

469
00:23:13,850 --> 00:23:15,020
feature.

470
00:23:15,020 --> 00:23:18,710
Each memory card
contains 128, 256,

471
00:23:18,710 --> 00:23:21,560
or 512 megabytes of
storage plus 8 bits

472
00:23:21,560 --> 00:23:25,400
of ECC for each 32-bit word,
providing a single-bit error

473
00:23:25,400 --> 00:23:28,190
correction and double-bit
error detection.

474
00:23:28,190 --> 00:23:29,720
A minimum of two
memory cards are

475
00:23:29,720 --> 00:23:33,290
needed to support the 1.28
gigabyte per second bandwidth

476
00:23:33,290 --> 00:23:35,630
capability of the global bus.

477
00:23:35,630 --> 00:23:37,550
To support atomic
synchronization between

478
00:23:37,550 --> 00:23:40,910
processors, we implemented
a read-lock/write-unlock

479
00:23:40,910 --> 00:23:44,150
mechanism, which allows a
processor to atomically lock

480
00:23:44,150 --> 00:23:46,820
out any location in global
memory from all other

481
00:23:46,820 --> 00:23:50,460
processors until unlocked
by that same processor.

482
00:23:50,460 --> 00:23:52,830
Using this simple
hardware primitive,

483
00:23:52,830 --> 00:23:55,830
we have implemented higher
level atomic functions,

484
00:23:55,830 --> 00:23:58,530
such as fetch-and-add
in software.

485
00:23:58,530 --> 00:24:01,380
While interleaved memory
banks provide an effective way

486
00:24:01,380 --> 00:24:04,480
of providing low latency access
to many processors making

487
00:24:04,480 --> 00:24:06,750
single read and write
requests, we also

488
00:24:06,750 --> 00:24:09,990
needed a mechanism to support
multiple hundred megabyte

489
00:24:09,990 --> 00:24:12,440
per second I/O channels.

490
00:24:12,440 --> 00:24:16,040
To do this we implemented a
fast, block DMA read feature

491
00:24:16,040 --> 00:24:18,020
in the global memory,
which supports

492
00:24:18,020 --> 00:24:20,540
the transfer of
contiguous blocks of data

493
00:24:20,540 --> 00:24:23,090
with a single
block read request.

494
00:24:23,090 --> 00:24:26,180
This design approach resulted
in a well-balanced design,

495
00:24:26,180 --> 00:24:28,190
providing low latency
and high bandwidth

496
00:24:28,190 --> 00:24:32,440
communication with a large
global memory subsystem.

497
00:24:32,440 --> 00:24:35,560
And finally, to support
high-speed I/O devices,

498
00:24:35,560 --> 00:24:38,140
we implemented a unique
audio processor card

499
00:24:38,140 --> 00:24:40,930
with four high-speed
HIPPI channels.

500
00:24:40,930 --> 00:24:44,260
Each I/O processor card contains
two HIPPI transmitters and two

501
00:24:44,260 --> 00:24:46,930
HIPPI receivers, each
capable of transferring

502
00:24:46,930 --> 00:24:48,850
100 megabytes per second.

503
00:24:48,850 --> 00:24:51,910
A dedicated processor
node identical to those

504
00:24:51,910 --> 00:24:54,520
on the processor cards
provides high-level control

505
00:24:54,520 --> 00:24:56,050
of the four HIPPI channels.

506
00:24:56,050 --> 00:24:58,600
It runs the I/O device
drivers and communicates

507
00:24:58,600 --> 00:25:00,670
through global memory
with client processes

508
00:25:00,670 --> 00:25:02,860
using remote procedure calls.

509
00:25:02,860 --> 00:25:05,470
I should mention that even
with all four channels running

510
00:25:05,470 --> 00:25:08,680
simultaneously, we have
measured sustained data transfer

511
00:25:08,680 --> 00:25:12,190
rates in excess of 320
megabytes per second

512
00:25:12,190 --> 00:25:15,630
from an application running
on the visualization server.

513
00:25:15,630 --> 00:25:19,140
Having described the hardware,
let me briefly describe the PVS

514
00:25:19,140 --> 00:25:20,730
operating system.

515
00:25:20,730 --> 00:25:23,940
The approach we took was to
implement a low-level kernel,

516
00:25:23,940 --> 00:25:27,120
which provides standard Unix
functions, such as process

517
00:25:27,120 --> 00:25:31,960
scheduling, virtual memory
protection, and standard I/O

518
00:25:31,960 --> 00:25:35,170
services, but without the
traditional multi-user

519
00:25:35,170 --> 00:25:38,860
multitasking implementation
techniques, which would not

520
00:25:38,860 --> 00:25:41,930
be effective for
real-time applications.

521
00:25:41,930 --> 00:25:44,750
Thus, the kernel does not
support demand paging.

522
00:25:44,750 --> 00:25:47,780
Everything must fit in local
memory and global memory.

523
00:25:47,780 --> 00:25:49,160
There is no task switching.

524
00:25:49,160 --> 00:25:52,640
Multiple users or tasks are
supported through partitioning,

525
00:25:52,640 --> 00:25:56,370
whereby, a process is giving a
chunk of processors and memory

526
00:25:56,370 --> 00:25:59,270
which remain static for
the duration of the task.

527
00:25:59,270 --> 00:26:02,480
We chose to support up to
eight simultaneous user tasks,

528
00:26:02,480 --> 00:26:04,880
given this would still
yield effective performance

529
00:26:04,880 --> 00:26:07,900
for each user.

530
00:26:07,900 --> 00:26:10,630
The application interface
consists of standard Unix

531
00:26:10,630 --> 00:26:16,420
libraries, including libc, libm,
and libX, with multiprocessor

532
00:26:16,420 --> 00:26:18,850
extensions to support
shared memory and processor

533
00:26:18,850 --> 00:26:20,230
synchronization.

534
00:26:20,230 --> 00:26:22,360
In addition, a
high-speed I/O library

535
00:26:22,360 --> 00:26:25,240
is provided to support the
high-speed disk array subsystem

536
00:26:25,240 --> 00:26:28,810
and frame buffer, including
support for a partition file

537
00:26:28,810 --> 00:26:31,990
system and movie utilities,
which allows an application

538
00:26:31,990 --> 00:26:36,580
to deal with movie sequences on
the disk array in a simple way.

539
00:26:36,580 --> 00:26:39,100
Let me conclude the
PVS technical summary

540
00:26:39,100 --> 00:26:41,710
by showing you some
performance numbers.

541
00:26:41,710 --> 00:26:45,100
First, let me talk about
theoretical peak performance

542
00:26:45,100 --> 00:26:48,160
numbers for the
32-processor server.

543
00:26:48,160 --> 00:26:50,980
At 40 megahertz,
each i860 processor

544
00:26:50,980 --> 00:26:53,710
is capable of delivering
40 MIPS and 80

545
00:26:53,710 --> 00:26:55,540
megaflops single precision.

546
00:26:55,540 --> 00:26:57,970
Thus, with simple
arithmetic, we can

547
00:26:57,970 --> 00:27:00,580
get a peak performance
of 1,280 MIPS

548
00:27:00,580 --> 00:27:03,760
and 2 and 1/2 gigaflops
single precision.

549
00:27:03,760 --> 00:27:05,740
Now, for some benchmarks.

550
00:27:05,740 --> 00:27:10,510
LINPACK TPP with a problem
size of 6,000 by 6,000 yields

551
00:27:10,510 --> 00:27:15,770
925 megaflops on a
32-processor server.

552
00:27:15,770 --> 00:27:20,200
A fast Fourier transform on
a 512 by 512 RGB color image

553
00:27:20,200 --> 00:27:23,620
sequence yields 10 frames per
second throughput from disk

554
00:27:23,620 --> 00:27:24,940
to display.

555
00:27:24,940 --> 00:27:27,580
This corresponds to an
actual throughput computation

556
00:27:27,580 --> 00:27:30,100
exceeding 700 megaflops.

557
00:27:30,100 --> 00:27:32,920
And finally, affine
transformations

558
00:27:32,920 --> 00:27:36,100
with rotate scale and
translate on a 512

559
00:27:36,100 --> 00:27:39,460
by 512 RGB color image
sequence achieves

560
00:27:39,460 --> 00:27:43,075
a throughput of 12 frames per
second from disk to display.

561
00:27:43,075 --> 00:27:47,240


562
00:27:47,240 --> 00:27:50,210
At this point, I have concluded
the technical overview

563
00:27:50,210 --> 00:27:52,278
of the Power
Visualization System.

564
00:27:52,278 --> 00:27:54,320
I would like to now give
you a brief introduction

565
00:27:54,320 --> 00:27:59,370
to Data Explorer, followed by
some demonstrations on the PVS.

566
00:27:59,370 --> 00:28:02,250
Data Explorer is a fully
integrated visualization tool

567
00:28:02,250 --> 00:28:06,150
which can deal with data from a
variety of application domains.

568
00:28:06,150 --> 00:28:08,010
It uses a visual
programming approach

569
00:28:08,010 --> 00:28:11,340
to define a visualization
program or network that

570
00:28:11,340 --> 00:28:15,090
imports raw data, performs a
series of realization functions

571
00:28:15,090 --> 00:28:19,230
on these data, and finally,
renders the resulting images.

572
00:28:19,230 --> 00:28:22,350
The tool contains nearly
100 visualization modules

573
00:28:22,350 --> 00:28:24,480
and uses an
object-oriented data model

574
00:28:24,480 --> 00:28:27,000
to represent data internally.

575
00:28:27,000 --> 00:28:29,880
Modules are written generically
to deal with various data

576
00:28:29,880 --> 00:28:32,340
types, and they
query the data model

577
00:28:32,340 --> 00:28:35,490
to figure out what to do
with the input data provided.

578
00:28:35,490 --> 00:28:38,010
For example, an
isosurface module

579
00:28:38,010 --> 00:28:40,620
will compute contour
lines given to the data,

580
00:28:40,620 --> 00:28:43,290
or an isosurface given 3D data.

581
00:28:43,290 --> 00:28:45,750
Unlike many other
visualization packages,

582
00:28:45,750 --> 00:28:49,380
Data Explorer is truly
domain-independent.

583
00:28:49,380 --> 00:28:52,140
Finally, Data Explorer
uses a client server model

584
00:28:52,140 --> 00:28:53,940
to support visualization.

585
00:28:53,940 --> 00:28:56,790
First of all, it runs
standalone at workstations,

586
00:28:56,790 --> 00:28:59,340
such as the IBM RS/6000.

587
00:28:59,340 --> 00:29:02,310
Second, the user interface
can run on one workstation

588
00:29:02,310 --> 00:29:04,920
while the server runs
on another workstation.

589
00:29:04,920 --> 00:29:06,540
And finally, the
server component

590
00:29:06,540 --> 00:29:09,060
can also run on the Power
Visualization System,

591
00:29:09,060 --> 00:29:12,090
thus providing the ability to
handle very large data sets

592
00:29:12,090 --> 00:29:16,320
and to realize complex
visualization techniques.

593
00:29:16,320 --> 00:29:18,870
I would now like to
introduce Lloyd Trenish, who

594
00:29:18,870 --> 00:29:21,180
is a research staff member
in the group specializing

595
00:29:21,180 --> 00:29:23,740
in a number of Earth
science problems.

596
00:29:23,740 --> 00:29:26,650
I'd like to talk to you about a
problem of scientific interest,

597
00:29:26,650 --> 00:29:28,320
or at least of great
interest to me,

598
00:29:28,320 --> 00:29:31,140
and that is one of ozone
depletion in the Earth's

599
00:29:31,140 --> 00:29:32,970
upper atmosphere.

600
00:29:32,970 --> 00:29:36,210
I've been using the
IBM Data Explorer

601
00:29:36,210 --> 00:29:39,030
software on the IBM Power
Visualization System

602
00:29:39,030 --> 00:29:42,190
to study that problem.

603
00:29:42,190 --> 00:29:46,770
What I'm showing here is
the total column ozone,

604
00:29:46,770 --> 00:29:48,870
as measured from
a NASA spacecraft,

605
00:29:48,870 --> 00:29:53,970
and it's being shown as
a spherical shell that's

606
00:29:53,970 --> 00:29:59,250
color- and opacity-mapped,
as well as radially deformed,

607
00:29:59,250 --> 00:30:01,320
all redundantly to show ozone.

608
00:30:01,320 --> 00:30:06,690
So the idea is that low ozone
values appear thin and closer

609
00:30:06,690 --> 00:30:09,480
to the Earth, and
higher ozone values,

610
00:30:09,480 --> 00:30:13,260
such as this ridge region
here, appears as further away

611
00:30:13,260 --> 00:30:15,870
from the Earth and thicker.

612
00:30:15,870 --> 00:30:19,590
The visualization Data
Explorer is really--

613
00:30:19,590 --> 00:30:23,580
is implemented to be able
to examine very large data

614
00:30:23,580 --> 00:30:24,360
problems.

615
00:30:24,360 --> 00:30:27,450
In this case, I'm dealing
with about a gigabyte's worth

616
00:30:27,450 --> 00:30:31,350
of data that exists
on the server.

617
00:30:31,350 --> 00:30:34,170
And I can interactively
browse and manipulate the data

618
00:30:34,170 --> 00:30:35,860
to study it in more detail.

619
00:30:35,860 --> 00:30:38,610
So let me show you some of
the features of this software,

620
00:30:38,610 --> 00:30:40,830
and all of the images
that you're seeing

621
00:30:40,830 --> 00:30:45,030
are being computed
as I'm talking

622
00:30:45,030 --> 00:30:49,840
in near real time on the server.

623
00:30:49,840 --> 00:30:52,410
So if I'm interested
in studying,

624
00:30:52,410 --> 00:30:55,380
let's say, this region where
we're looking at the ozone

625
00:30:55,380 --> 00:30:57,510
depletion, and this
is during the spring,

626
00:30:57,510 --> 00:31:01,950
the Antarctic spring
October in 1987.

627
00:31:01,950 --> 00:31:06,330
I've taken a profile
along this line

628
00:31:06,330 --> 00:31:09,570
to take a look at the
structure of the polar vortex,

629
00:31:09,570 --> 00:31:12,750
this circulation phenomenon
that you're seeing here.

630
00:31:12,750 --> 00:31:14,640
And the structure
is very pronounced,

631
00:31:14,640 --> 00:31:17,040
and we see the depletion region.

632
00:31:17,040 --> 00:31:22,330
If I'm now interested in
studying that in more detail,

633
00:31:22,330 --> 00:31:24,840
I've been able to implement
through the Data Explorer

634
00:31:24,840 --> 00:31:30,000
a number of tools to allow me
to try different techniques

635
00:31:30,000 --> 00:31:34,680
to literally apply a
"what if" kind of notion

636
00:31:34,680 --> 00:31:37,475
towards examining data
sets such as this.

637
00:31:37,475 --> 00:31:39,600
So now I'm only looking at
the southern hemisphere,

638
00:31:39,600 --> 00:31:42,720
and I can see the structure
of the depletion region

639
00:31:42,720 --> 00:31:48,690
and the circulation of the polar
vortex around the South Pole.

640
00:31:48,690 --> 00:31:50,910
What would be of
interest is that we

641
00:31:50,910 --> 00:31:53,460
know the depletion
occurs in the late '80s

642
00:31:53,460 --> 00:31:54,960
and still occurs today.

643
00:31:54,960 --> 00:31:58,500
What did it look like before
the ozone hole was discovered,

644
00:31:58,500 --> 00:32:01,740
let's say, in the early '80s?

645
00:32:01,740 --> 00:32:07,920
Right now, I'm telling the Data
Explorer through this interface

646
00:32:07,920 --> 00:32:11,820
that I've built with the tools
that it provides that I now

647
00:32:11,820 --> 00:32:13,980
want to look at 1983.

648
00:32:13,980 --> 00:32:16,800
So interactively, I've
gone out and I've grabbed

649
00:32:16,800 --> 00:32:18,570
another year's worth of data.

650
00:32:18,570 --> 00:32:23,610
And I'm immediately creating
the same kind of visualization

651
00:32:23,610 --> 00:32:25,650
that I looked at for 1987.

652
00:32:25,650 --> 00:32:29,800
And I can do an easy comparison
visually in this fashion.

653
00:32:29,800 --> 00:32:32,160
We can see a similar
structure associated

654
00:32:32,160 --> 00:32:37,920
with the polar vortex, but a
much less pronounced depletion

655
00:32:37,920 --> 00:32:38,790
region.

656
00:32:38,790 --> 00:32:42,300
Now traditionally, a
workstation couldn't

657
00:32:42,300 --> 00:32:46,110
allow me to interactively
manipulate a gigabyte data set.

658
00:32:46,110 --> 00:32:50,470
But the visualization Data
Explorer software and the Power

659
00:32:50,470 --> 00:32:53,070
Visualization System
have really been

660
00:32:53,070 --> 00:32:56,610
designed to scale to
these types of data sets,

661
00:32:56,610 --> 00:33:00,040
to deal with complexity,
including, for example,

662
00:33:00,040 --> 00:33:01,940
missing data.

663
00:33:01,940 --> 00:33:03,280
After all, these are real data.

664
00:33:03,280 --> 00:33:05,200
These are observations.

665
00:33:05,200 --> 00:33:09,910
And also in order to gain
the performance that's

666
00:33:09,910 --> 00:33:12,940
required to manipulate
these data quickly,

667
00:33:12,940 --> 00:33:14,800
to perform the kinds
of transformations

668
00:33:14,800 --> 00:33:18,340
and rendering to take advantage
of the parallel architecture

669
00:33:18,340 --> 00:33:23,470
in the shared memory of the PVS.

670
00:33:23,470 --> 00:33:25,450
The capabilities
of Data Explorer

671
00:33:25,450 --> 00:33:28,990
have allowed me to combine these
different observational data

672
00:33:28,990 --> 00:33:30,430
sets.

673
00:33:30,430 --> 00:33:34,870
I've been interested in studying
the problem of ozone depletion

674
00:33:34,870 --> 00:33:37,150
and how it relates to the
dynamics of the Earth's

675
00:33:37,150 --> 00:33:38,530
upper atmosphere.

676
00:33:38,530 --> 00:33:42,190
But until I could really
use the Power Visualization

677
00:33:42,190 --> 00:33:45,290
System to combine these
data sets and work with

678
00:33:45,290 --> 00:33:49,000
them interactively was
I able to determine

679
00:33:49,000 --> 00:33:50,800
that there may be a
relationship between

680
00:33:50,800 --> 00:33:54,100
upper tropospheric dynamics
and the stratospheric ozone

681
00:33:54,100 --> 00:33:55,180
depletion.

682
00:33:55,180 --> 00:33:58,780
And this kind of
capability, this horsepower

683
00:33:58,780 --> 00:34:04,300
to interactively pose
a problem and look

684
00:34:04,300 --> 00:34:07,720
at a potential
correlation, has been

685
00:34:07,720 --> 00:34:10,683
very exciting, very gratifying
to me as a scientist.

686
00:34:10,683 --> 00:34:13,350


687
00:34:13,350 --> 00:34:16,020
I hope you've enjoyed these
demonstrations and introduction

688
00:34:16,020 --> 00:34:19,469
to the IBM Power Visualization
System and Data Explorer.

689
00:34:19,469 --> 00:34:21,900
We believe the PVS
and Data Explorer

690
00:34:21,900 --> 00:34:25,800
offer an innovative solution
to interactive visualization.

691
00:34:25,800 --> 00:34:28,650
Together, they pave the
way to a new paradigm

692
00:34:28,650 --> 00:34:30,210
in technical computing--

693
00:34:30,210 --> 00:34:33,540
the ability to interact
with a computer simulation,

694
00:34:33,540 --> 00:34:36,330
while simultaneously
visualizing the results.

695
00:34:36,330 --> 00:34:39,000
I would like to thank all the
individuals that contributed

696
00:34:39,000 --> 00:34:40,980
to the success of this project.

697
00:34:40,980 --> 00:34:42,870
We learned that when
you bring together

698
00:34:42,870 --> 00:34:46,290
a team of highly motivated
and diversified people

699
00:34:46,290 --> 00:34:49,989
and allow them to be creative,
the sky is the limit.

700
00:34:49,989 --> 00:34:51,822
Thank you.

701
00:34:51,822 --> 00:34:52,770
Outstanding.

702
00:34:52,770 --> 00:34:53,720
Yeah, that was great.

703
00:34:53,720 --> 00:34:54,220
Good.

704
00:34:54,220 --> 00:34:57,570
[MUSIC PLAYING]

705
00:34:57,570 --> 00:35:51,000