By clicking the download links, you acknowledge that you have read and agree to the Software Licensing Agreement below.
If you use Heracles in your research, we would appreciate the following citation in any publications to which it has contributed:
Michel A. Kinsy, Michael Pellauer, and Srinivas Devadas: "Heracles: A Tool for Fast RTL-Based Design Space Exploration of Multicore Processors." In Proceedings of the 21st International Symposium on Field Programmable Gate Arrays (FPGA), February 2013 [bib]
- Heracles Designer v2.0 release notes is on the Wiki page.
- Heracles Designer v2.0 - It is the complete system with graphic user interface, Verilog files, and software toolchain.
- Standalone hardware system - It has all the synthesizable Verilog files of the Heracles system.
- Standalone software system - User should move it into a Linux environment.
Copyright (c) 2015 Heracles (CSG/CSAIL/MIT - CAES Lab/UO). Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
