Second Workshop on
Computer Architecture and Operating System
In conjunction with:
the 6th ACM International Conference on
High-Performance Embedded Architectures and Compilers (HiPEAC'11)
Heraklion, Crete, Greece, January 24-26, 2011
- Jan 22nd, 2011: The workshop proceedings now available online.
- Jan 4th, 2011: The workshop program is now available here.
- Jan 4th, 2011: We are pleased to announce that Prof. Margaret Martonosi (Princeton University) will be delivering the keynote for the second edition of the CAOS workshop on "Reexamining TLB Design for Modern Chip Multiprocessors". The abstract of her talk is available here.
Multi-core and/or multi-threaded architectures are monopolizing the market, from embedded systems to supercomputers. However, extracting high performance from these modern systems has become a complex task. As the number of cores per chip and/or the number of hardware threads per core continue to increase, new research questions arise in scheduling, power, temperature, scalability, design complexity, efficiency, throughput, heterogeneity, etc. Performance is not the only important metric anymore, and new metrics (such as security, power, total throughput, reliability and Quality of Service) are becoming more and more important. Therefore, it is evident that neither hardware nor software alone can achieve the desired performance and, at the same time, be compliant with these constraints. One approach to tackle these new challenges comes from hardware-software co-design.
This workshop aims to bring together researchers and engineers from academia and industry to share ideas and research directions in Computer Architecture and Operating System co-design and interaction. Authors are invited to submit innovative manuscripts in all areas of parallel and distributed processing, real-time systems, HPC systems and commercial/server systems.
Papers are sought on topics including, but not limited to:
- Architectural and OS support for power and thermal management
- Architectural and OS support for scheduling applications on emerging multi-core systems
- Benchmarking and characterization of OS activity in multi-core architectures
- Architectural and OS support for virtualization
- Architectural and OS support to manage processor resource allocation and heterogeneity for Quality of Service
- Simulation tools for full system simulation
The workshop provides a forum to discuss the latest proposals in co-designing the computer architecture, software systems and OS and to bring ideas and research problems to the attention of the audience. Papers reporting on on-going work that address cross-cutting issues and provide thought-provoking insights into the main themes are encouraged to submit their work. Position and Vision papers are also welcomed. Papers Proceedings with accepted papers will be made available at the workshop and possible indexing with ACM. All Accepted papers will be considered for a best paper award, which will be announced at the workshop and the best paper will be considered for publication in a special issues of the HiPEAC workshop proceedings.
Updated on Jan 4th, 2011.
|Session I Chair: Professor Angelos Bilas|
Keynote: Reexamining TLB Design for Modern Chip Multiprocessors
Prof. Margaret Martonosi (Princeton University)
The performance of Translation Lookaside Buffers is a very important factor in overall program performance, with TLB misses often representing 10% or more of program runtime. Despite this, their design issues remained largely unexamined as the transition from single-core to multi-core processors occurred. This talk will describe my group's recent body of work to characterize and optimize TLB behavior for Chip Multiprocessors. Considering both parallel workloads and also multiprogrammed workloads of sequential applications, we have proposed a range of techniques that can reduce TLB misses by more than 20% on average, with only modest hardware requirements. I will discuss hardware and software tradeoffs in the implementation of these ideas, as well as the methodological challenges of quantifying TLB performance effects. This talk will include many of our recent PACT '09, ASPLOS '10, and HPCA '11 results, and represents joint work with Abhishek Bhattacharjee and Dan Lustig.
|Session II Chair: Professor Dimitris Nikolopoulos|
|11.00-11.30||System-level Optimizations for Memory Access in the Execution Migration Machine (EM2)
Keun Sup Shim (MIT), Mieszko Lis (MIT), Myong Hyon Cho (MIT), Omer Khan (MIT), Srinivas Devadas (MIT)
|11.30-12.00||Power-Performance Adaptation in Intel Core i7
Vasileios Spiliopoulos (Uppsala University), Georgios Keramidas (Industrial Systems Institute), Stefanos Kaxiras (Uppsala University), Konstantinos Efstathiou (University of Patras)
|12.00-12.30||A Sleep-based Communication Mechanism to Save Processor Utilization in Distributed Streaming Systems
Shoaib Akram (FORTH-ICS), Angelos Bilas (FORTH-ICS)
|12.30-14.00||Closing and lunch|
|Abstracts submission deadline:||Oct. 29th 2010 11:30PM PST|
|Papers submission deadline:||Oct. 31th 2010 11:30PM PST|
|Notification to authors:||Dec. 6th 2010|
|Final version of accepted papers:||Dec. 20th 2010|
|HiPEAC Conference:||Jan 24-26th, 2011|
|Workshop:||Jan 22nd, 2011|
Submitted papers should use the LNCS format and should be 10 pages maximum. Manuscript preparation guidelines can be found at the LNCS web site.
In order to submit your paper go to Here .
|Roberto Gioiosa||Barcelona Supercomputing Center||Spain||roberto.gioiosa[_at_]bsc.es|
|Lamia Youseff||MIT, CSAIL||USA||lyouseff[_at_]csail.mit.edu|
|Omer Khan||MIT, CSAIL||USA||okhan[_at_]csail.mit.edu|
|Buyuktosunoglu, Alper||(IBM T.J. Watson, USA)|
|Cazorla, Francisco||(BSC, Spain)|
|Cesati, Marco||(U. of Rome Tor Vergata, Italy)|
|da Silva, Dilma||(IBM T.J. Watson, USA)|
|Etsion, Yoav||(Barcelona Supercomputing Center, Spain)|
|Hoffmann, Henry||(MIT, USA)|
|Holt, Jim||(Freescale, USA)|
|Kursun, Eren||(IBM T.J. Watson, USA)|
|McKee, Sally||(Chalmers University of Technology, Sweden)|
|Minnich, Ronald||(Sandia National Lab, USA)|
|Pakin, Scott||(LANL, USA)|
|Tsafrir, Dan||(Technion, Israel)|
|Villa, Oreste||(PNNL, USA)|
|Wisniewski, Robert||(IBM T.J. Watson, USA)|